PCIe Interface Power Mode Control for Latency Management
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Solution Overview
Problem
In electronic devices, the PCIe interface's power mode transitions cause latency issues that degrade delay-sensitive services like VR and AR, while increasing power consumption, necessitating a method to manage latency and power consumption effectively.
Innovation Solution
An electronic device with a first integrated circuit and a second integrated circuit connected via a PCIe interface, where the first integrated circuit identifies the required latency level and restricts the use of PCIe power modes based on that level to optimize power management and service quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the PCIe interface uses power mode transitions (L0, L0s, L1, L2, L3) to reduce power consumption, then power consumption is reduced, but latency increases and service quality degrades
Solution Approach 1:
The patent dynamically adjusts the PCIe interface power mode based on real-time service requirements. The processor identifies the latency requirements of active services and selectively transitions the PCIe interface between different power modes (L0, L0s, L1, L2, L3), allowing the system to optimize power consumption while maintaining service quality by adapting to changing operational conditions.
Solution Approach 2:
The patent changes the power mode parameter of the PCIe interface based on service latency requirements. By monitoring service characteristics and adjusting the power mode parameter accordingly, the system can switch between low-power states (L2, L3) when latency requirements are lenient and high-performance states (L0, L0s) when low latency is required, thus resolving the contradiction between power consumption and latency.
2Reliability
If the PCIe interface remains in active power mode to maintain low latency, then service quality is maintained, but power consumption increases
Solution Approach 1:
The system dynamically determines the appropriate power mode by continuously monitoring service latency requirements. When services with strict latency requirements are detected, the PCIe interface maintains active power modes (L0, L0s) to ensure service quality. When no such services are active, the system transitions to lower power modes (L1, L2, L3), thereby reducing power consumption while maintaining service quality when needed.
Solution Approach 2:
The patent adjusts the power mode parameter based on service quality requirements. The processor identifies latency requirements of running services and selectively changes the PCIe interface power mode parameter, allowing the system to maintain high performance (L0/L0s) when service quality is critical and reduce power consumption (L1/L2/L3) when services can tolerate higher latency or are not latency-sensitive.
Data Source
AI summary
An apparatus and method for controlling an interface between a plurality of processors in an electronic device are disclosed. The electronic device may include: a first integrated circuit; a second integrated circuit; and a Peripheral Component Interconnect Express (PCIe) interface interconnecting the first integrated circuit and the second integrated circuit, wherein the first integrated circuit may be configured to identify the required latency level associated with a service provided by the electronic device, and restrict the use of at least one power mode among a plurality of power modes supported by the PCIe interface, based on the required latency level associated with the service. Additional embodiments are possible.