Hardware RAID Acceleration for PCIe Transaction Coalescing
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Solution Overview
Problem
The PCIe bus in current information handling systems experiences duplication of upstream and downstream transactions, leading to increased data transmission times and latency, which reduces bandwidth capacity and increases system latency due to multiple PCIe endpoints accessing the same physical/machine memory address.
Innovation Solution
A hardware logic device is introduced to receive command fetch requests from multiple memory storage devices, analyze metadata to serialize these requests, and coalesce them into chronological order before communicating them to a memory with stored commands, thereby eliminating redundant transactions and optimizing data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple PCIe endpoints access the same physical memory address concurrently, then device versatility and parallel processing capability are improved, but transaction duplication occurs resulting in increased latency and reduced bandwidth capacity
Solution Approach 1:
A hardware logic device is introduced as an intermediary between multiple PCIe endpoints and the memory system. This device receives command fetch requests from multiple endpoints, analyzes their metadata, serializes them in chronological order, and coalesces duplicate requests before forwarding to memory. The intermediary eliminates transaction duplication while preserving concurrent access capability, thereby reducing latency without sacrificing bandwidth capacity.
Solution Approach 2:
The hardware logic device merges multiple command fetch requests into a single coalesced request when they target the same memory address. By combining duplicate upstream and downstream transactions, the system reduces the total number of memory accesses required, eliminating redundant data transmission while maintaining the functional capability of multiple endpoints accessing the same memory location.
2Productivity
If multiple PCIe endpoints access the same physical memory address, then system parallelism is improved, but transaction duplication reduces bandwidth capacity
Solution Approach 1:
The hardware logic device acts as a bandwidth optimization intermediary that monitors and manages transactions from multiple PCIe endpoints. It identifies and coalesces duplicate requests, ensuring that parallel processing operations do not result in redundant memory accesses. This preserves the productivity benefits of parallelism while optimizing bandwidth utilization and reducing energy consumption associated with redundant data transmission.
Solution Approach 2:
The system changes the parameter of transaction serialization by analyzing metadata and ordering requests chronologically before memory access. This parameter change allows the system to maintain parallel processing capability at the endpoint level while ensuring sequential, non-duplicative access to memory, thereby optimizing bandwidth capacity without sacrificing productivity.
3Speed
If command fetch requests are processed in parallel from multiple storage devices, then processing speed is improved, but out-of-order transactions increase system latency
Solution Approach 1:
The hardware logic device performs preliminary action by analyzing metadata from command fetch requests before they are processed by the memory system. It pre-sorts and serializes requests in chronological order, ensuring that even though requests arrive in parallel from multiple storage devices, they are processed in the correct sequence. This preliminary organization eliminates out-of-order latency while preserving the speed benefits of parallel request generation.
Data Source
AI summary
In accordance with embodiments of the present disclosure, a method of transmitting data in an information handling system may include receiving, at a hardware logic device from a plurality of memory storage devices communicatively coupled to the hardware logic device, a plurality of command fetch requests; analyzing metadata associated with each of the plurality of command fetch requests in order to serialize the plurality of command fetch requests in a chronological order; and communicating the coalesced command fetch requests in the chronological order to a memory having stored thereon commands responsive to the coalesced command fetch requests.