PCI Express Data Receiving Buffer for Asynchronous Packet Storage
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Solution Overview
Problem
The PCI Express standard's data transfer mechanism, particularly with a lane width of 16 lanes, poses a challenge in simultaneously storing headers and data link layer packets due to their asynchronous input, leading to difficulties in storing reception history effectively.
Innovation Solution
A data receiving apparatus is designed with a history unit that includes a buffer and a processing unit to temporarily store data link layer packets and write them to a history storage when headers and data link layer packets are acquired simultaneously or when only the data link layer packet is available, ensuring both can be stored correctly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the PCI Express standard's data transfer mechanism is used with 16 lanes, then the data transfer rate is increased, but the asynchronous input of headers and data link layer packets makes simultaneous storage difficult
Solution Approach 1:
The patent applies preliminary action by pre-storing the data link layer packet in a buffer when it is received, before the header is fully processed. This allows the header and packet to be stored together even though they arrive asynchronously at different times, resolving the contradiction between high-speed data transfer and simultaneous storage requirements
Solution Approach 2:
The buffer acts as an intermediary element between the asynchronous data reception and the history storage mechanism. It temporarily holds the data link layer packet until the header is available, enabling coordinated storage of both components without requiring complex synchronization mechanisms
2Device complexity
If headers and data link layer packets are stored separately, then the storage structure is simple, but the reception history cannot be accurately represented
Solution Approach 1:
The patent merges the storage of headers and data link layer packets into a unified history storage structure. By combining these previously separate storage locations into a single coherent history that preserves the association between headers and their corresponding packets, the system maintains simple storage architecture while ensuring accurate reception history representation
Data Source
AI summary
A data receiving apparatus includes: a memory; and a processor coupled to the memory and the processor configured to: extract reception data, a header of a transaction layer packet, and a data link layer packet which are included in a received reception signal; store the data link layer packet in a buffer; store the header of the transaction layer packet and the data link layer packet in a history storage; write the data link layer packet to the buffer when the header of the transaction layer packet and the data link layer packet are simultaneously acquired; write the data link layer packet stored in the buffer to the history storage when the header of the transaction layer packet and the data link layer packet is not acquired or when the data link layer packet is acquired without acquiring the header of the transaction layer packet.