PCIe Refclk Early Indicator for Fast PLL Lock
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Solution Overview
Problem
Current PCIe devices experience significant latency and power consumption issues during transitions between power management states, particularly when waking up from low-power states, due to the serialization of lock times for phase-locked loops (PLLs), which can exceed system tolerance and disable power-saving features.
Innovation Solution
A bus protocol compatible device provides a reference clock signal (Refclk) as an early in-band indicator to linked devices, allowing them to parallelize their transitions and reduce overall lock time to the longer of the two PLL lock times, thereby facilitating faster wake-up and power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PCIe devices wait for PLL lock completion before transitioning to active state, then clock synchronization is ensured, but wake-up latency increases significantly
Solution Approach 1:
The transmitter provides the reference clock signal (Refclk) as an early indicator before the device completes its internal PLL lock. This preliminary action allows the linked device to begin its transition to active state earlier, reducing wake-up latency while ensuring clock synchronization is achieved by the time full communication begins.
Solution Approach 2:
The linked device receives the Refclk signal and begins its PLL lock process in advance, before the transmitting device has fully completed its own lock. This parallel processing of clock synchronization reduces the overall wake-up time for the link while maintaining reliability.
2Use of energy by moving object
If PCIe devices power down PLLs to save power, then energy consumption decreases, but transition time to active state increases
Solution Approach 1:
By providing Refclk as an early indicator, the system enables the linked device to start its PLL lock process before full activation is required. This allows the device to power down PLLs during low-power states and still achieve fast transition by having the clock signal ready to immediately drive the PLL upon wake-up.
Solution Approach 2:
The wake-up process is segmented into distinct phases: Refclk signal provision, PLL lock acquisition, and full active state transition. This segmentation allows power management to control different stages independently, enabling power-down of non-critical circuits while maintaining the essential clock signal path for fast recovery.
3Reliability
If PCIe devices serialize their PLL lock processes, then clock synchronization is maintained, but overall link activation time increases
Solution Approach 1:
The transmitting device provides Refclk as a preliminary signal that triggers the linked device's PLL lock process in advance. This allows both devices to perform their clock synchronization operations in parallel rather than sequentially, significantly reducing overall link activation time while maintaining synchronization reliability.
Data Source
AI summary
A bus protocol compatible device includes an encoder having an input for receiving a local clock signal, and an output, a multiplexer having a first input for receiving a reference clock signal, a second input coupled to said output of said encoder, a control input for receiving a select signal, and an output, and a driver having an input coupled to said output of said multiplexer, and an output for coupling to a bus protocol link.