PCIe Data Regeneration with Synchronized Link Equalization
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Solution Overview
Problem
Existing digital communication systems, such as repeaters, ritimers, and packet switches, require additional circuitry and consume more power due to their enhanced functionality, leading to increased area and power consumption in integrated circuit implementations.
Innovation Solution
A data regeneration device that performs upstream and downstream link equalization procedures in compliance with the PCIe 3.0 protocol, transitioning seamlessly between low-speed and high-speed modes, and synchronizing these procedures to reduce the need for switching functions and protocol implementation, thereby minimizing circuitry and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a retimer device performs synchronization function in addition to regenerating function, then signal integrity is improved by removing jitter, but power consumption and circuit area increase
Solution Approach 1:
The patent segments the retimer functionality into separate upstream and downstream processing paths, allowing independent optimization of each direction's equalization and synchronization operations, reducing overall power consumption while maintaining signal integrity
Solution Approach 2:
The patent implements dynamic equalization adjustment where the equalization settings are automatically optimized based on the actual signal quality and transmission distance, allowing the device to use minimal processing power while achieving the required signal integrity level
2Adaptability or versatility
If a packet switch performs switching function in addition to regenerating and synchronizing functions, then data routing capability is improved, but power consumption and circuit area increase
Solution Approach 1:
The patent extracts the switching function from the regenerator device, implementing it as a separate packet switch component. This allows the regenerator to focus solely on signal integrity while the switch handles routing, optimizing the overall system power consumption and area usage
3Reliability
If link equalization procedures are performed on both upstream and downstream data links, then signal quality is improved, but device complexity increases
Solution Approach 1:
The patent merges the control logic for upstream and downstream equalization procedures into a unified control mechanism that coordinates both directions simultaneously, reducing device complexity while ensuring signal quality on both links through synchronized equalization adjustment
Data Source
AI summary
A data regeneration device regenerates a digital signal in a low-speed pass-through mode of operation, performs an upstream link equalization procedure on an upstream data link in an equalization mode of operation, performs a downstream link equalization procedure on a downstream data link in the equalization mode of operation, and regenerates the digital signal in a high-speed pass-through mode of operation. The data regeneration device transitions seamlessly from the low-speed pass-through mode of operation to the equalization mode of operation in compliance with a communication protocol. Moreover, the data regeneration device synchronizes completion of the upstream link equalization procedure with completion of the downstream link equalization procedure so that the data regeneration device transitions seamlessly from the equalization mode of operation to the high-speed pass-through mode of operation in compliance with the communication protocol.