PCIe Retimer Bypass Path for Low-Latency Power Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
PCIe retimers in low latency mode consume excessive power due to unnecessary operations, particularly when lane skew is negligible, leading to inefficiencies in high-speed data transmission.
Innovation Solution
Implement a retimer with a bypass path that bypasses clock domain components in the downstream and upstream paths, enabling a low latency mode by disabling unnecessary clock signals through a controller, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the retimer operates in low latency mode by bypassing clock domain components, then latency is reduced, but power consumption increases due to unnecessary operations
Solution Approach 1:
The retimer dynamically switches between two operational paths: a full processing path with clock domain components for normal operation, and a bypass path for low latency mode. The controller selectively enables or disables clock signals to clock domain components based on the operational mode, allowing the system to adapt its power consumption and latency characteristics to current needs.
Solution Approach 2:
The bypass path extracts and removes the clock domain components from the signal path when low latency mode is activated. By taking out these components from the critical data path, the retimer eliminates the latency introduced by clock domain crossings while the controller manages power consumption by disabling clocks to removed components.
2Ease of operation
If the retimer maintains readiness to exit low latency mode at any moment, then latency responsiveness is improved, but power consumption remains high
Solution Approach 1:
The system maintains dynamic controllability by keeping the controller active and monitoring for mode transition commands. The controller can rapidly enable or disable clock signals to clock domain components, allowing quick transitions between operational modes while minimizing the time components spend in high-power states.
Solution Approach 2:
The bypass path is pre-configured and ready for immediate activation when low latency mode is commanded. The controller maintains the ability to quickly enable the bypass path and disable clock signals without requiring gradual transitions, achieving rapid responsiveness while minimizing power consumption during mode switching.
Data Source
AI summary
An illustrative retimer includes: an upstream interface having an upstream receiver configured to convert a downlink signal into a downlink symbol stream; a downstream interface having a downstream transmitter configured to provide a transmit signal representing the downlink symbol stream; core circuitry having a downstream path and a downstream bypass path; and a controller. The downstream path is configured to convey the downlink symbol stream from the upstream receiver to the downstream transmitter via a receive clock domain component, a core clock domain component, and a transmit clock domain component. The downstream bypass path is configurable to convey the downlink symbol stream from the upstream receiver to the downstream transmitter without any core clock domain components. The controller is configured to disable a clock signal for the transmit clock domain component of the downstream path when the downstream bypass path is enabled.