PCIe Retimer Clock-Domain Merging for Low-Latency Data Transfer
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Solution Overview
Problem
In PCIe SRIS scenarios, the use of retimers introduces latency due to the need to add or delete SKP sequences to compensate for frequency differences between transmit and receive ends, leading to system performance losses, especially in applications like PCIe memory scenarios.
Innovation Solution
A drive and data transmission method that employs a clock and data recovery (CDR) circuit, elastic buffer, receiver circuit, and transmitter circuit, all operating in the same clock domain, eliminating the need for SKP sequence adjustments by synchronizing the receive and transmit clocks, thus reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a retimer is applied in an SRIS scenario to compensate for frequency differences, then frequency synchronization is improved, but latency is increased due to SKP sequence additions or deletions
Solution Approach 1:
The patent extracts and eliminates the SKP sequence insertion/deletion mechanism from the data transmission path. By using a unified receive clock for both elastic buffer operations and transmitter circuit clocking, the system removes the need for latency-inducing SKP sequences while maintaining frequency compensation functionality.
Solution Approach 2:
The patent merges the clock domains by using the receive clock directly for both the elastic buffer read/write operations and the transmitter circuit clocking. This unification of clock sources eliminates the frequency mismatch that previously required SKP sequences, thereby reducing latency while maintaining synchronization.
2Device complexity
If separate reference clocks with independent SRIS are used in the PCIe bus, then design complexity is reduced and costs are reduced, but frequency differences between transmit and receive ends cause latency when retimers are added
Solution Approach 1:
The patent makes the receive clock serve multiple functions simultaneously: it clocks the elastic buffer for data storage/retrieval, it clocks the transmitter circuit for data transmission, and it provides the reference for frequency compensation. This multi-functionality eliminates the need for separate transmit and receive clocks, maintaining the simplicity of SRIS while avoiding latency.
3Reliability
If SKP sequences are added or deleted to compensate for frequency differences, then data synchronization is maintained, but system performance is lost especially in PCIe memory scenarios
Solution Approach 1:
The patent performs preliminary synchronization by using the receive clock to pre-align the elastic buffer operations and transmitter circuit clocking before data transmission begins. This preliminary action ensures that no SKP sequences are needed during actual data transmission, thereby maintaining synchronization while maximizing performance.
Data Source
AI summary
This application provides a drive and a data transmission method, to implement low-latency transmission. The drive includes a CDR circuit, an elastic buffer, a receiver circuit, and a transmitter circuit. The CDR circuit is configured to recover a receive clock from a received signal. The receiver circuit is configured to recover sent data from the received signal by using the receive clock. The elastic buffer is configured to move the sent data in by using the receive clock and move the data out by using the receive clock. The transmitter circuit is configured to send the sent data from the elastic buffer by using the receive clock.