PCIe Retimer Low Latency Data Path Switching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
PCIe retimers introduce significant latency due to processing steps during signal regeneration, which degrades performance in systems with multiple retimers, especially when signals pass through connectors and printed circuit boards, causing reflections and inter-symbol-interference.
Innovation Solution
A PCIe retimer with in-band low latency switching logic that monitors read commands of vendor registers to switch between a link training data path and a low latency data path, bypassing training components after initial link training, allowing direct data transfer without external control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full PCIe physical layer stack processing is used for signal regeneration, then signal integrity is improved, but latency increases significantly
Solution Approach 1:
The patent segments the PCIe data path into two distinct paths: a full processing path for link training that includes all receiver and transmitter logic, and a low-latency path for normal data transfer that bypasses processing steps. This segmentation allows the system to use comprehensive processing only when needed for signal integrity during training, while using the streamlined path for routine operations to minimize latency.
Solution Approach 2:
The patent implements dynamic switching between processing modes based on operational state. During link training, the full PCIe physical layer stack is activated to ensure signal integrity. Once training is complete, the system dynamically transitions to the low-latency path that bypasses unnecessary processing steps, achieving adaptive optimization of both signal integrity and latency based on real-time requirements.
2Length of stationary object
If multiple retimers are used to extend PCIe bus range, then connectivity is improved, but round-trip latency increases
Solution Approach 1:
Each retimer in the chain is segmented to provide both full processing capability for link training and a low-latency bypass path for normal operations. This allows multiple retimers to be cascaded to extend bus range while each retimer contributes minimal latency during data transfer, as the low-latency paths are activated once training is complete.
Solution Approach 2:
Link training is performed preliminarily through all retimers in the chain using the full processing path, establishing signal integrity across the extended bus range. Once training is complete, the low-latency paths are activated in advance for all subsequent operations, preventing latency accumulation during normal data transfer even though multiple retimers are present.
3Loss of time
If in-band switching logic is implemented for low latency mode, then latency is reduced, but device complexity increases
Solution Approach 1:
The in-band switching logic is integrated into the existing PCIe retimer architecture, allowing the same hardware components to serve dual functions: full processing during link training and low-latency bypass during normal operations. This multi-functionality reduces the need for separate dedicated switching hardware, thereby limiting the increase in device complexity while achieving latency reduction.
Solution Approach 2:
The switching between full processing mode and low-latency mode is performed automatically by in-band switching logic that monitors operational state without requiring external control signals. The retimer self-manages the mode transitions based on internal state detection, eliminating the need for complex external control circuitry and reducing overall system complexity while maintaining low latency performance.
Data Source
AI summary
A PCIe retimer includes read-only vendor registers with low latency mode entry and exit values. In-band low latency switching logic monitors the output of an elastic buffer for read commands of the vendor registers and, when such read commands are received, reads the corresponding address and switches a multiplexer between a link training data path and a low latency data path based on the return value of the read operation. Read commands, and therefore control of data path switching, is handled entirely in-band. Return values of the read operations indicate success or failure of mode switching to the root complex.