PCIe Riser Card Auto-Configuration via CPLD Detection
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Solution Overview
Problem
Conventional server systems employing Slimline x8 connectors and PCIe cables face issues with misconnection of PCIe ports to riser cards of incompatible sizes, leading to improper operation due to the use of identical cables, especially in systems with a large number of PCIe ports.
Innovation Solution
A circuit structure with automatic PCIe lane configuration adjustment, which includes a motherboard with a CPLD module, storage unit, BMC module, and BIOS unit, that reads PCIe size identifiers from riser cards via PCIe cables and adjusts lane configurations based on predefined information, allowing for flexible connection of PCIe ports to riser cards as long as total lane and card counts match predefined settings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PCIe slot configuration information is pre-stored in EEPROM to determine lane counts, then the system can properly identify installed PCIe devices, but the PCIe port must be connected to a riser card with the same number of lanes, limiting flexibility
Solution Approach 1:
The invention performs preliminary detection of the actual connected riser card's lane configuration during system initialization, before the operating system allocates PCIe slots. The CPLD module detects the lane counts of actually connected riser cards and stores this information in a register, enabling the system to adapt to the actual connection configuration rather than relying on pre-stored fixed configuration information.
Solution Approach 2:
The invention transforms the static, fixed PCIe lane configuration into a dynamic, adaptive configuration. The system can automatically adjust and recognize different lane configurations (x4, x8, x16) based on the actual riser card connections, allowing the same PCIe port to work with different riser card types without manual reconfiguration or hardware changes.
2Area of stationary object
If multiple Slimline x8 connectors are used as PCIe ports to save space, then more connectors can be accommodated on the motherboard, but the risk of misconnection increases due to identical cables being used
Solution Approach 1:
The invention implements a feedback mechanism where the CPLD module continuously monitors and detects the actual lane configuration of connected riser cards. This feedback information is used to dynamically adjust the PCIe lane allocation, ensuring that the system operates correctly regardless of which specific riser card is connected to which PCIe port, thereby eliminating the need for users to match specific ports with specific riser cards.
Solution Approach 2:
The system performs self-configuration by automatically detecting the lane counts of connected riser cards and adjusting its own PCIe lane allocation accordingly. The CPLD module and BIOS work together to automatically configure the appropriate number of lanes for each PCIe port based on the actual hardware connections, without requiring user intervention or manual configuration.
3Device complexity
If PCIe lane configuration is fixed by pre-stored information, then the system structure is simple, but the system cannot work properly when connected to riser cards with different lane counts
Solution Approach 1:
The invention changes the key parameter of PCIe lane configuration from a fixed, pre-stored value to a dynamically detectable and adjustable value. The CPLD module detects the actual lane counts of connected riser cards and modifies the PCIe lane allocation parameters accordingly, enabling the system to support multiple lane configurations (x4, x8, x16) with the same hardware structure.
Data Source
AI summary
A circuit structure with automatic PCIe lane configuration adjustment and a method thereof are disclosed. The circuit structure includes a plurality of PCIe riser cards and a motherboard. The PCIe riser cards are of at least two lane sizes each associated with a PCIe size identifier. The motherboard includes a plurality of PCIe ports, a CPLD module, a storage unit, a BMC module and a BIOS unit. The PCIe ports are electrically connected to the respective PCIe riser cards via a plurality of PCIe cables. The CPLD module is electrically connected to the PCIe ports so as to be able to read the PCIe size identifiers thereof and determine current configuration information from a comparison between the PCIe size identifiers and present signals. The storage unit stores predefined PCIe configuration information, and the BMC module is configured to issue a match signal when finding a match between the current configuration information and the predefined PCIe configuration information, thus allowing booting of the BIOS unit.