PCIe Riser Reset Signal Synchronization for Multi-Die Systems
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Information handling systems face challenges in synchronizing reset signals from multiple dies to PCIe risers, leading to potential configuration corruption and link failures when different dies are coupled to the same PCIe slot, affecting system performance.
Innovation Solution
The information handling system firmware aggregates and synchronizes reset signals from multiple dies to PCIe risers, providing de-assertion signals to prevent configuration corruption and ensure seamless link training across multiple dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If reset signals from multiple dies are provided to PCIe risers without synchronization, then each die can operate independently, but configuration corruption and link failures occur
Solution Approach 1:
The patent introduces an intermediary synchronization mechanism that receives reset signals from multiple dies, aggregates them, and provides synchronized reset signals to PCIe risers. This intermediary layer prevents configuration corruption and link failures by ensuring proper signal timing, while maintaining independent die operation.
Solution Approach 2:
The patent merges multiple reset signals from different dies into a single synchronized signal path. By combining the reset assertions and de-assertions from multiple dies through an aggregation mechanism, the system ensures that PCIe risers receive coordinated reset signals, preventing configuration corruption that would occur with unsynchronized signals.
2Adaptability or versatility
If multiple dies are coupled to the same PCIe slot, then system functionality is enhanced, but link width downgrades and failures occur due to unsynchronized reset signals
Solution Approach 1:
The patent implements preliminary synchronization of reset signals before they are provided to PCIe risers. By pre-aggregating and synchronizing the reset signals from multiple dies before distribution, the system ensures that link training and configuration processes occur reliably, preventing link width downgrades and failures that would otherwise occur with unsynchronized signals.
3Ease of operation
If reset de-assertion signals are provided to PCIe risers without synchronization, then system operation is simplified, but configuration corruption occurs
Solution Approach 1:
The patent implements a feedback mechanism where the system monitors reset signal status from multiple dies and dynamically adjusts the synchronization and aggregation of reset de-assertion signals. This feedback-based approach ensures that configuration integrity is maintained by providing properly synchronized de-assertion signals to PCIe risers, preventing configuration corruption while managing signal complexity automatically.
Data Source
AI summary
In one or more embodiments, one or more systems, methods, and/or processes may receive a first signal from information handling system firmware; may provide, based at least on the first signal, each of first multiple reset assertion signals to each of respective multiple Peripheral Component Interconnect Express (PCIe) risers, each of the multiple PCIe risers including multiple PCIe slots; may receive second multiple reset assertion signals from respective multiple dies, each of the multiple dies includes at least one processing core and at least one PCIe root complex; may receive a second signal from the information handling system firmware; may determine that the second multiple reset assertion signals and the second signal were received; and may, after determining that the second multiple signals and the second signal were received, provide each of third multiple reset de-assertion signals to a respective PCIe riser of the multiple PCIe risers.