PCIe Root Complex Memory Transaction Coalescing
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Solution Overview
Problem
Current information handling systems face increased data transmission times and latency due to duplication of transactions on the PCIe bus, which reduces bandwidth capacity and increases system latency when multiple PCIe endpoints access the same physical/machine memory address.
Innovation Solution
A hardware logic device detects memory transaction requests from PCIe devices and coalesces requests with the same system memory address into a common transaction request, reducing redundant operations and improving data transmission efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple PCIe endpoints access the same physical memory address independently, then each endpoint can operate autonomously, but data transmission time increases and latency increases due to duplicated transactions
Solution Approach 1:
The patent merges duplicate memory transaction requests from multiple PCIe endpoints into a single coalesced request when they target the same physical memory address. The root complex detects duplicate requests and combines them, reducing the number of transactions to system memory while maintaining autonomous endpoint operation. This resolves the contradiction by combining requests (improving time efficiency) while preserving endpoint independence (maintaining reliability).
2Reliability
If multiple PCIe endpoints independently transact with system memory, then endpoint autonomy is maintained, but PCIe bandwidth capacity decreases due to transaction duplication
Solution Approach 1:
The root complex merges duplicate transactions from multiple PCIe endpoints into single memory transactions when they target the same physical address. This coalescing mechanism increases effective PCIe bandwidth by eliminating redundant transactions while preserving endpoint autonomy through intelligent request consolidation at the root complex level.
3Reliability
If duplicate memory transaction requests are processed separately, then each endpoint's request is handled independently, but system latency increases
Solution Approach 1:
The root complex detects and merges duplicate memory transaction requests from multiple PCIe endpoints that target the same physical memory address. By coalescing these requests into a single transaction, the system reduces latency while maintaining independent request handling semantics, as each endpoint's request is still processed but through a consolidated path.
Data Source
AI summary
An information handling system (IHS) and a method of transmitting data in an IHS. The method includes detecting, via a hardware logic device, a first memory transaction request from a first peripheral component interconnect express (PCIe) device to a system memory. The first memory transaction request includes a first system memory address. A second memory transaction request is detected from a second PCIe device to the system memory. The second memory transaction request includes a second system memory address. The method further includes determining if the first system memory address and the second system memory address are the same system memory address. In response to the first and second system memory addresses being the same, the first memory transaction request and the second memory transaction request are coalesced into a common memory transaction request. The common memory transaction request is issued to the system memory.