PCIe Segment Identifier for MCTP Addressability

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Solution Overview

Problem

Current server platforms face challenges in managing a large number of PCIe buses due to the limitations of the Management Component Transport Protocol (MCTP) over PCIe, which can only address up to 256 buses, leading to address exhaustion and the need for additional hardware or modifications to support more than 256 buses.

Innovation Solution

The implementation of a method that uses a segment identifier to extend the addressability of PCIe buses beyond 256 by combining endpoint identifiers with segment identifiers within the MCTP packet format, allowing routing across multiple PCIe bus segments without requiring extra hardware or changes to existing endpoints.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If MCTP over PCIe is used to manage PCIe buses, then high bandwidth and low latency communication is achieved, but address exhaustion occurs when more than 256 buses are present

Engineering Contradiction:

Improvecommunication speedVSAvoidaddressability

Core Design Contradiction:

SpeedVSAdaptability or versatility

Solution Approach 1:

The patent introduces a new dimension to the addressing scheme by adding a PCIe bus segment identifier to the MCTP packet format. This extends the address space from 256 buses to over 65,000 buses by combining the segment identifier with the existing bus number and endpoint identifier fields, thereby resolving the address exhaustion problem while maintaining high-speed PCIe communication.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Speed

If a dedicated sideband bus is used for manageability applications, then high bandwidth and low latency communication is achieved, but component costs increase and motherboard placement options are limited

Engineering Contradiction:

Improvecommunication speedVSAvoidhardware complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent makes the existing PCIe bus serve multiple functions: it not only carries standard PCIe transactions but also transports MCTP management traffic through the Vendor Defined Message (VDM) mechanism. This eliminates the need for a separate dedicated sideband bus, reducing hardware complexity and cost while maintaining high-performance communication for manageability applications.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Ease of manufacture

If internal busses are used for manageability communication, then component integration is improved, but mix and match configurations are limited

Engineering Contradiction:

Improvecomponent integrationVSAvoidconfiguration flexibility

Core Design Contradiction:

Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent introduces MCTP over PCIe VDM as an intermediary communication mechanism that bridges the BMC and various PCIe endpoints. This standard-based intermediary layer enables flexible configuration and communication across different PCIe devices without requiring proprietary internal busses or fixed motherboard layouts, thereby supporting mix-and-match configurations while maintaining strong integration.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS9411762B2Method and system for platform management messages across peripheral component interconnect express (PCIe) segments

Publication Date: 2016.08.09 TAHOE RES LTD

AI summary

A method is disclosed to manage platform management messages through multiple peripheral component interconnect express (PCIe) segments implemented on a root complex of a computing system.