PCIe Hardware Sequencer for Time-Critical CXL Link Training
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Solution Overview
Problem
The implementation of the Compute Express Link (CXL) protocol over PCIe introduces latency issues due to strict timing requirements in communication link training, which existing memory sub-system controllers struggle to meet, particularly during critical performance periods like startup or firmware upgrades.
Innovation Solution
A memory sub-system initiates PCIe link training using a hardware sequencer that programs parameter values to registers, allowing it to participate in communication link training independently of the controller, reducing the controller's time-sensitive operations and enabling timely compliance with industry specifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the controller handles PCIe link training operations, then the memory sub-system can maintain protocol compliance, but the controller becomes overloaded during critical periods like startup or firmware upgrades
Solution Approach 1:
The patent divides the PCIe link training functionality into two separate components: a hardware sequencer that handles time-sensitive link training operations independently, and a controller that manages higher-level memory sub-system operations. This segmentation allows the controller to offload latency-critical tasks to dedicated hardware, maintaining protocol compliance without overloading the controller during startup or firmware upgrades.
Solution Approach 2:
The hardware sequencer acts as an intermediary component between the controller and the PCIe link training process. It receives initialization parameters from the controller, then autonomously executes the time-sensitive link training sequence with the host system, and finally reports completion back to the controller. This intermediary architecture isolates the controller from real-time timing constraints while ensuring protocol compliance through coordinated operation.
2Reliability
If the controller performs time-sensitive link training operations, then communication compliance is achieved, but downtime increases during critical periods
Solution Approach 1:
The hardware sequencer is pre-configured with link training parameters and initialization data before the actual link training begins. The controller prepares and loads these parameters into the sequencer's registers in advance, so that when link training is triggered, the hardware can execute the sequence immediately without waiting for the controller to process each step in real-time, thereby reducing downtime during startup.
Solution Approach 2:
The patent replaces the software-based link training execution in the controller with a dedicated hardware sequencer that operates autonomously. This hardware implementation executes link training operations in parallel with other controller activities, eliminating the sequential processing bottleneck and reducing the time the system remains non-operational during critical startup or firmware upgrade periods.
3Adaptability or versatility
If firmware is updated in the controller, then new functionality is achieved, but PCIe communication compliance may be compromised due to timing constraints
Solution Approach 1:
By separating link training execution from firmware processing, the patent allows firmware to be updated in the controller without affecting the hardware sequencer's ability to execute time-sensitive link training operations. The hardware sequencer maintains dedicated logic and registers for link training that remain independent of firmware changes, ensuring PCIe communication compliance is preserved even as controller firmware evolves to add new functionality.
Data Source
AI summary
A first set of parameter values are programed to a first set of sequencer registers. A second set of parameter values are programmed to a second set of sequencer registers. In response to a detecting a triggering event, a hardware sequencer performs the following operations: transfer the first set of parameter values from the first set of sequencer registers to a first set of link training registers, transfer the second set of parameter values from the second set of sequencer registers to a second set of link training registers, and initiate one end of a communication link training with a host.