PCIe Shock Absorber Buffer for Simplified TLP Processing
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Solution Overview
Problem
The complexity of PCIe Transaction Layer Packet (TLP) processing logic increases with larger data bus widths due to multiple TLPs fitting within a single clock cycle, especially when multiple TLPs of the same type are received, requiring complex processing paths and doubling the overhead in chip technology nodes with multi-write port arrays.
Innovation Solution
Implementing a 'Shock Absorber Buffer' (SAB) between the PCIe Data Link Layer and Transaction Layer to control the flow of TLPs, allowing only one TLP per clock cycle, using a feedback path to manage overflow scenarios and issue PCIe replays when necessary, simplifying processing logic and reducing pipeline complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If larger data bus widths are used to handle inbound data stream, then data transmission capacity is improved, but TLP processing logic becomes more complex
Solution Approach 1:
A shock absorber buffer is introduced as an intermediary component between the data link layer and transaction layer. This buffer receives multiple TLPs from the data link layer and releases them to the transaction layer at a controlled rate of one TLP per clock cycle, thereby decoupling the high-speed data transmission from the complex processing logic and simplifying the transaction layer design.
Solution Approach 2:
The processing function is segmented into two distinct stages: (1) a data link layer that captures multiple TLPs in parallel, and (2) a shock absorber buffer that sequentially releases them one at a time to the transaction layer. This segmentation allows the data link layer to maximize bandwidth while the transaction layer maintains simple, predictable processing logic.
2Productivity
If multiple TLPs are processed per clock cycle, then processing throughput is improved, but pipeline complexity increases
Solution Approach 1:
The shock absorber buffer acts as a mediator between the data link layer and transaction layer, receiving multiple TLPs in parallel and releasing them sequentially at one per clock cycle. This eliminates the need for complex parallel processing pipelines while maintaining high throughput by buffering multiple packets for sequential processing.
3Adaptability or versatility
If buffer size is increased to handle overflow, then data handling capability is improved, but device complexity increases
Solution Approach 1:
A feedback mechanism is implemented where the shock absorber buffer signals the data link layer when it is full, causing the data link layer to request a replay. This feedback loop allows the system to handle overflow scenarios automatically without requiring excessively large buffers or complex error handling logic, as the replay mechanism naturally manages buffer capacity constraints.
Data Source
AI summary
A computer-implemented method, a computer system and a computer program product simplify PCIe Transaction Layer Packet (TLP) processing logic. The method includes providing a buffer in a PCIe processing environment between a data link layer and a transaction layer, wherein the buffer includes a maximum buffer size and a command interface to the data link layer. The method also includes storing PCIe data from the data link layer in the buffer and identifying a transaction layer packet in stored PCIe data. The method further includes forward the transaction layer packet from the buffer, where a transaction layer packet is forwarded to the transaction layer for each clock cycle in the plurality of clock cycles of the PCIe processing environment. Lastly, the method includes determining that the maximum buffer size has been reaches and notifying the data link layer using the command interface to initiate a PCIe replay.