PCI-Express Power Management Snooping Circuit
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Solution Overview
Problem
Peripheral devices in computer systems using the PCI-Express bus cannot enter a power-saving mode simultaneously due to the lack of a power management unit, leading to degraded transmission rates when high-bandwidth devices like SATA or gigabit networks are used, as they share limited bandwidth with the South Bridge chip.
Innovation Solution
Implementing a snooping and blocking process via a snooping circuit or program in the first system chip to retrieve and manage power-saving commands, allowing peripheral devices coupled with both North and South Bridge chips to enter a power-saving mode synchronously by snooping and blocking signals between the CPU and system chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If PCI-Express bus is used for high-bandwidth devices like SATA or gigabit network, then transmission rate is improved, but bandwidth sharing with South Bridge chip causes transmission rate degradation
Solution Approach 1:
The patent segments the power management control by introducing a snooping circuit in the North Bridge chip that can intercept and process power-saving commands independently. This allows the North Bridge chip to manage power states of devices connected to it separately from the South Bridge chip, eliminating the bandwidth sharing bottleneck while maintaining high transmission rates.
2Device complexity
If power-saving mode is implemented without snooping and blocking processes, then power management is simplified, but peripheral devices cannot enter power-saving mode simultaneously
Solution Approach 1:
The patent introduces an intermediary snooping circuit in the North Bridge chip that mediates power-saving commands between the CPU and peripheral devices. This circuit intercepts power-saving commands, processes them locally, and coordinates with the South Bridge chip to ensure all devices enter power-saving mode simultaneously, achieving reliable synchronous power management without excessive complexity.
3Use of energy by moving object
If L2 or L3 power mode is defined without snooping process, then power saving is achieved, but CPU and system chips cannot coordinate power-saving commands properly
Solution Approach 1:
The patent implements preliminary action by having the snooping circuit in the North Bridge chip intercept and process power-saving commands before they reach the South Bridge chip. This allows the North Bridge chip to prepare and coordinate power-saving states in advance, ensuring proper synchronization and command coordination while maintaining effective power savings through L2/L3 power modes.
Data Source
AI summary
A computer system and a method of signal transmission via a PCI-Express bus is provided for transmitting a power-saving signal among a plurality of peripheral devices. For the peripheral devices coupled with the system chips can enter a power-saving mode successfully, a signal snooping and blocking manners are introduced into the system chips. The present invention is to improve on a problem that the system chips cannot enter the power-saving mode simultaneously since the system chips don't set any power-management unit therein.