PCIe SRIO Protocol Controller Atomic Operation Bypass
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Solution Overview
Problem
Existing SRIO fabrics do not support Direct Single Access (DSA) or atomic transfers with commercially available root complexes, particularly PCI-Express standard does not directly support atomic operations, limiting system throughput in data storage systems.
Innovation Solution
The implementation of a data storage system with a PCIE/SRIO protocol controller that includes a DSA section for low latency transfers, allowing DSA requests to bypass conventional store-forward packet buffers and utilize a master DSA and slave DSA architecture to perform atomic operations efficiently across a packet switching network.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional store-forward packet buffers are used in SRIO fabrics, then system stability is maintained, but transfer latency increases and throughput is limited
Solution Approach 1:
The patent segments the packet buffer functionality into two distinct paths: a conventional store-forward path for standard packets and a bypass path for DSA atomic operations. This segmentation allows critical atomic operations to skip the buffering stage entirely, achieving low-latency direct access while maintaining the stability-providing store-forward mechanism for other traffic.
Solution Approach 2:
The patent introduces a DSA atomic operation engine as an intermediary component that sits between the SRIO fabric and the root complex. This engine intercepts atomic operation requests, performs them directly without involving the conventional packet buffers, and returns results immediately, thereby eliminating the latency bottleneck while preserving system stability through the intermediary's controlled access.
2Productivity
If PCI-Express standard is used without atomic operation support, then device compatibility is maintained, but system throughput is limited
Solution Approach 1:
The patent implements a universal DSA atomic operation engine that handles multiple types of atomic operations (read, write, compare-and-swap, fetch-and-add) through a single unified hardware structure. This multi-functional engine works across different SRIO fabric configurations and root complex implementations, providing broad compatibility while enabling high-throughput atomic operations that enhance overall system productivity.
3Ease of operation
If atomic operations are performed through conventional packet switching, then protocol compatibility is maintained, but transfer efficiency decreases
Solution Approach 1:
The patent extracts the atomic operation processing function from the conventional packet switching path and places it in a dedicated DSA atomic operation engine. This extraction allows atomic operations to bypass the complex packet buffering, arbitration, and forwarding mechanisms, achieving simple and efficient direct access. The engine maintains protocol compatibility by presenting a standardized interface while internally using a simplified execution model that dramatically improves transfer efficiency.
Data Source
AI summary
A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.