PCIe/SRIO Protocol Controller Atomic Operation Bypass
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Solution Overview
Problem
Existing SRIO fabrics do not support Direct Single Access (DSA) or atomic transfers with commercially available root complexes, particularly PCI-Express standard does not directly support atomic operations, limiting system throughput in data storage systems.
Innovation Solution
The implementation of a data storage system with a PCIE/SRIO protocol controller that includes a DSA section for low latency transfers, allowing DSA requests to bypass conventional store-forward packet buffers and enabling atomic operations by using a master DSA to initiate operations on a slave DSA through a packet switching network, ensuring high priority and minimal latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional store-forward packet buffers are used in SRIO fabrics, then packet switching network stability is improved, but transfer latency increases and system throughput decreases
Solution Approach 1:
The patent segments the packet handling path into two types: conventional store-forward path for normal packets and a bypass path for DSA packets. The DSA section creates a dedicated direct access pathway that segments away from the main store-forward buffer chain, allowing critical DSA transfers to bypass the latency-introducing buffers while regular traffic continues through the stable store-forward path.
Solution Approach 2:
The DSA section acts as an intermediary component between the root complex and the packet switching network. It mediates DSA requests by intercepting them before they enter the conventional store-forward buffer path and routing them through a direct bypass path, thus eliminating latency without compromising the stability of the main network path.
2Adaptability or versatility
If PCI-Express protocol is used without atomic operation support, then device compatibility is improved, but system functionality is limited
Solution Approach 1:
The DSA section serves as an intermediary that adds atomic operation capability to the PCI-Express interface without requiring changes to the root complex or end devices. It translates PCI-Express transactions into atomic operations supported by the packet switching network, enabling enhanced functionality while maintaining broad device compatibility.
Solution Approach 2:
The DSA section provides multi-functionality by handling both conventional PCI-Express transactions and atomic operations through a single interface. It universally supports both types of operations, allowing the system to maintain compatibility with standard PCI-Express devices while also enabling advanced atomic operations for improved productivity.
3Device complexity
If DSA transfers are implemented without bypass capability, then system complexity is reduced, but transfer speed decreases
Solution Approach 1:
The patent segments the transfer path into standard and bypass routes. The DSA section implements a relatively simple bypass mechanism that segments critical DSA transfers from the main data flow, providing low-latency paths without requiring complex reconfiguration of the entire system architecture.
Solution Approach 2:
The bypass capability is implemented locally at the DSA section rather than system-wide. This localized approach provides high-speed direct access where needed (for DSA transfers) while leaving the rest of the system architecture unchanged, thus achieving speed improvement with minimal added complexity.
Data Source
AI summary
A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.