PCIe/SRIO Protocol Controller Atomic Transfer Bypass
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Solution Overview
Problem
Existing SRIO fabrics do not support Direct Single Access (DSA) or atomic transfers with commercially available root complexes, limiting the system throughput in data storage systems.
Innovation Solution
The implementation of a data storage system with a PCIE/SRIO protocol controller that includes a DSA section, allowing for low latency DSA transfers by bypassing conventional store-forward packet buffers and using a master DSA to initiate atomic operations on a slave DSA, optimizing DSA performance through cut-through buffering and priority routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional store-forward packet buffers are used in SRIO fabrics, then device complexity is reduced, but system throughput is limited due to latency and congestion
Solution Approach 1:
The patent extracts the DSA transfer mechanism from the conventional store-forward packet buffer system. By implementing a separate DSA section with cut-through buffering that bypasses the traditional packet buffer queue, the system eliminates the latency and congestion issues associated with conventional buffering while maintaining manageable complexity through modular design
Solution Approach 2:
The patent implements preliminary action through the master DSA initiating atomic operations on slave DSA before data transfer completes. The cut-through buffering mechanism prepares packets in advance and allows them to be forwarded immediately without waiting for buffer availability, reducing latency and improving throughput
2Reliability
If DSA transfers are implemented without atomic operations support, then device complexity is reduced, but reliability of data storage operations deteriorates
Solution Approach 1:
The patent merges the DSA transfer mechanism with atomic operation support within the same DSA section. The master DSA and slave DSA work together to perform atomic read-modify-write operations, ensuring data consistency and reliability while keeping the implementation integrated and manageable
Solution Approach 2:
The patent implements feedback mechanisms where the master DSA receives status information from the slave DSA after atomic operations complete. This feedback loop ensures proper synchronization and reliability by confirming that atomic operations have been executed successfully before proceeding to the next operation
Data Source
AI summary
A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.