PCIE SRIO Protocol Controller Atomic Operations
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Solution Overview
Problem
Existing SRIO fabrics do not support Direct Single Access (DSA) or atomic transfers with commercially available root complexes, particularly PCI-Express standard does not directly support atomic operations, limiting system throughput in data storage systems.
Innovation Solution
The implementation of a data storage system with a PCIE/SRIO protocol controller that includes a DSA section, allowing for low latency DSA transfers by bypassing conventional store-forward packet buffers, and utilizing a master DSA and slave DSA architecture to perform atomic operations across the packet switching network.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional store-forward packet buffers are used in SRIO fabric, then packet transfer is supported, but atomic operations and direct single access transfers are not enabled, limiting system throughput
Solution Approach 1:
The patent segments the packet switching network into two distinct paths: conventional store-forward packet buffers for general packet transfer, and a dedicated direct single access (DSA) path for atomic operations. This segmentation allows atomic operations to bypass the conventional buffering mechanism, enabling them to access memory directly without waiting for packet buffer availability, thereby achieving both high throughput and atomic operation support simultaneously
Solution Approach 2:
The patent introduces a DSA section as an intermediary component between the packet switching network and memory. This intermediary enables direct single access transfers by providing a dedicated pathway that mediates between the conventional packet buffer system and the memory access requirements, allowing atomic operations to occur without interfering with normal packet transfer operations
2Ease of manufacture
If PCI-Express standard is used for root complex, then commercial availability is ensured, but atomic operations are not directly supported, reducing system performance
Solution Approach 1:
The patent creates a universal packet switching network architecture that serves multiple functions: it handles conventional packet transfer through store-forward buffers, enables atomic operations through the DSA section, and maintains compatibility with PCI-Express root complexes. This multi-functionality allows the system to leverage the commercial availability and simplicity of PCI-Express while achieving advanced atomic operation performance through the integrated DSA capability
Solution Approach 2:
The patent nests the DSA section within the existing packet switching network architecture, embedding the atomic operation capability inside the conventional network infrastructure. The DSA section is integrated into the packet switching fabric, allowing atomic operations to be performed within the existing system framework without requiring a complete architectural replacement, thus maintaining commercial availability while enhancing performance
3Reliability
If store-forward packet buffers are used, then packet transfer is reliable, but latency increases for atomic operations requiring immediate access
Solution Approach 1:
The patent segments packet transfer into two independent pathways: one through store-forward buffers for reliable but less latency-sensitive transfers, and another through direct single access for latency-critical atomic operations. This segmentation allows each pathway to be optimized for its specific requirements, maintaining reliability for general packet transfer while eliminating latency for atomic operations that use the dedicated DSA path
Solution Approach 2:
The patent extracts the latency-sensitive atomic operation functionality from the conventional store-forward packet buffer system and places it in a separate direct single access pathway. By taking out atomic operations from the general packet transfer mechanism, the system can provide immediate access without being constrained by the reliability-oriented store-forward buffering, thus reducing latency while maintaining overall system reliability
Data Source
AI summary
A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.