PCIE/SRIO Protocol Controller DSA Bypass
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Solution Overview
Problem
Existing SRIO fabrics do not support Direct Single Access (DSA) or atomic transfers with commercially available root complexes, particularly due to limitations in PCI-Express and RIO standards, which hinder efficient data transfer operations in data storage systems.
Innovation Solution
The implementation of a data storage system with a PCIE/SRIO protocol controller that includes a DSA section, allowing for low-latency DSA transfers by bypassing conventional store-forward packet buffers and utilizing a master DSA and slave DSA architecture to manage atomic operations within a packet switching network.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional store-forward packet buffers are used in SRIO fabrics, then packet switching network stability is maintained, but data transfer latency increases and throughput decreases
Solution Approach 1:
The patent extracts the DSA transfer function from the conventional store-forward packet buffering path and creates a separate direct access path. The DSA section bypasses the normal packet buffer infrastructure, allowing direct CPU-to-remote-memory access without intermediate buffering, thereby eliminating the latency penalty associated with store-forward operations while maintaining system throughput.
Solution Approach 2:
The patent introduces a DSA section as an intermediary component between the CPU and remote memory across the packet switching network. This intermediary provides specialized direct access capabilities that bridge the gap between conventional SRIO fabric limitations and the need for low-latency atomic transfers, enabling efficient DSA operations without disrupting the stability of the existing packet switching infrastructure.
2Adaptability or versatility
If PCI-Express and RIO standards are strictly followed, then device compatibility is maintained, but DSA and atomic transfer capabilities are lost
Solution Approach 1:
The patent segments the protocol controller functionality by introducing a dedicated DSA section that operates independently from the conventional SRIO fabric interface. This segmentation allows the system to maintain compliance with standard PCI-Express and RIO protocols for general operations while adding specialized DSA and atomic transfer capabilities through the separate DSA section, thereby increasing adaptability without excessively complicating the overall device architecture.
Solution Approach 2:
The protocol controller is designed with multi-functionality, serving both as a conventional SRIO interface and as a DSA engine. The DSA section can operate independently to provide direct access transfers and atomic operations, while also working in conjunction with the standard SRIO fabric for regular packet switching, thereby achieving versatility across multiple transfer modes without requiring separate dedicated hardware for each function.
3Productivity
If master DSA and slave DSA architecture is implemented, then atomic operations efficiency is improved, but system complexity increases
Solution Approach 1:
The patent merges the master DSA and slave DSA functionalities into a unified DSA section architecture. Rather than implementing completely separate master and slave controllers, the design combines both roles within the same hardware block, allowing a single DSA section to function as master when initiating transfers and as slave when receiving transfers. This merging approach improves atomic operations throughput by providing dedicated hardware support while controlling system complexity through architectural integration.
Data Source
AI summary
A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller passes a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.