PCIE SSD Status Light Control via CPLD Mediator
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Solution Overview
Problem
Conventional methods for controlling the status indication light of PCIE solid-state hard disks do not allow real-time determination of their usage status, as the CPU cannot control the light, unlike SATA/SAS hard disks.
Innovation Solution
A method and system that determine the current operation mode of a PCIE hard disk, transmit this information to a southbridge chip and a complex programmable logic device (CPLD), and use Hamming check codes to ensure accurate display control of the status indication light, enabling real-time usage status determination through a determining module, transmitting modules, and a control module.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the conventional operation mode of PCIE SSD is used with unshared pins in SFF-8639 connector, then the connector can provide exclusive access for SATA/SAS hard disk and PCIE SSD, but the CPU cannot control the status indication light of the PCIE SSD
Solution Approach 1:
The patent introduces a southbridge chip as an intermediary component between the CPU and the PCIE SSD. The southbridge chip receives operation mode information from the CPU and transmits it to the CPLD, which then controls the status indication light. This mediator enables CPU control of the status light without requiring direct connection or changing the connector architecture.
2Ease of operation
If the CPU directly controls the status indication light as in SATA/SAS hard disks, then real-time usage status can be determined, but the PCIE SSD architecture with unshared pins cannot support this control method
Solution Approach 1:
The southbridge chip serves as a mediator that enables CPU control of the status indication light without requiring direct CPU-CPLD connection. The southbridge chip receives operation mode information from the CPU and forwards it to the CPLD, which then controls the LED. This approach maintains the existing PCIE SSD architecture while enabling real-time status determination.
Solution Approach 2:
The control function is segmented into multiple components: the CPU determines operation mode, the southbridge chip transmits the information, and the CPLD controls the actual LED display. This segmentation allows each component to perform its specific function while maintaining the overall system architecture.
3Ease of operation
If operation mode information is transmitted through the southbridge chip to CPLD, then the CPU can control the status indication light, but additional transmission steps are required
Solution Approach 1:
The southbridge chip is pre-configured with the capability to receive and forward operation mode information between the CPU and CPLD. The transmission path is established in advance, allowing rapid information transfer when control is needed without setting up additional communication channels during operation.
Data Source
AI summary
A method and a system for controlling a status indication light of a Peripheral Component Interconnect Express (PCIE) hard disk are disclosed. The method includes determining a current operation mode of the PCIE hard disk and transmitting information of the current operation mode to a southbridge chip by a CPU. The information is transmitted to a complex programmable logic device (CPLD) by the southbridge chip. The display of the status indication light corresponding to the current operation mode is controlled according to the information by the complex programmable logic device. The CPLD is controlled by the southbridge chip, to control display control of the status indication light corresponding to reset and locate operation of the PCIE hard disk. The usage status of the PCIE hard disk may be determined in real time by performing Hamming check to the information, and the accurate display of status indication light may be ensured.