PCIe SSD Fast Boot Through Preliminary Lane Training
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Solution Overview
Problem
Existing memory sub-systems face challenges in achieving fast boot times, particularly when using SSDs instead of flash memory for booting, as accessing boot partitions from SSDs takes longer than from traditional flash memory, necessitating a more efficient mechanism.
Innovation Solution
Implementing a new configuration space register in PCIe devices to define boot configurations, allowing for fast boot capabilities by using SSDs, which includes a field to indicate fast or normal boot and specific parameters for communication link settings, enabling rapid boot firmware loading and training of PCIe lanes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If SSDs are used instead of flash memory for booting, then cost efficiency is improved and device integration is enhanced, but boot time increases due to slower access to boot partitions
Solution Approach 1:
The patent performs preliminary actions by training PCIe lanes at reduced speeds and loading essential boot firmware before the host system fully boots. This preliminary boot firmware is stored in the SSD and executed first to establish basic system functionality, allowing the system to become operational faster while still using the SSD for booting. The configuration space register is also prepared in advance with boot configuration values that guide this preliminary boot process.
Solution Approach 2:
The boot process is segmented into multiple phases: a preliminary boot phase using boot firmware loaded from the SSD via PCIe, and a subsequent full boot phase. The boot firmware itself is segmented into essential components that can be executed quickly without requiring full SSD initialization. This segmentation allows the system to separate time-critical boot functions from non-critical initialization tasks.
2Loss of time
If traditional flash memory is used for booting, then boot time is reduced due to fast access to boot partitions, but device integration is limited and cost efficiency decreases
Solution Approach 1:
The patent extracts the boot firmware from the host system's traditional boot media and places it directly in the SSD's memory space. This allows the SSD to serve dual purposes: as the primary storage device and as the boot device, eliminating the need for separate flash memory. The boot configuration value in the configuration space register enables the host system to locate and execute this extracted boot firmware directly from the SSD.
Solution Approach 2:
The SSD is given multiple functions: it serves as both the primary storage device and the boot device. The PCIe interface is also made multi-functional, supporting both data transfer and boot firmware execution. The configuration space register structure is designed to support both traditional and PCIe-based boot modes, making the system universally compatible with different boot scenarios while preferentially enabling SSD-based booting.
3Power
If PCIe lanes are trained at full speed during boot, then communication performance is optimized, but boot time increases due to longer training duration
Solution Approach 1:
The PCIe lane training speed is made dynamic rather than static. During the preliminary boot phase, lanes are trained at reduced speeds to minimize training time and enable faster boot. Once the boot firmware is executed and the system transitions to the full boot phase, the PCIe lanes are re-trained or re-configured to operate at full speed for optimal communication performance. This dynamic adjustment of training speed resolves the contradiction between fast boot and communication performance.
Solution Approach 2:
The PCIe lane training is performed periodically in distinct phases: first a rapid preliminary training at reduced speed for boot firmware loading, then a subsequent full-speed training for normal operation. This periodic re-training approach allows the system to optimize for different operational requirements at different times, achieving both fast boot and high communication performance.
Data Source
AI summary
A system can include a memory device; and a processing device, operatively coupled with the memory device, to perform operations including: receiving, from a host system connected to the memory device, a first reset signal; determining whether a first value stored in a configuration space of the memory device indicates a fast boot; responsive to determining that the first value indicates the fast boot, loading a fast boot firmware from the memory device, wherein the fast boot firmware allows the processing device to access a boot partition of the memory device; and responsive to receiving a request from the host system, retrieving boot data from the boot partition.