PCIe SSD Fault Analysis via Remote Controller Registers
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Solution Overview
Problem
Current methods for fault analysis in solid-state drives (SSDs) are inadequate when the NVMe device cannot be detected by the host, as external serial ports and debugging tools are not typically connected in mass-produced products, making it difficult to obtain useful information for diagnosis.
Innovation Solution
A method utilizing PCIe configuration space registers to remotely obtain fault information by writing a flag to a designated address, monitoring for the flag, writing fault information in batches to another address, and updating offset addresses, allowing the host to retrieve and analyze the information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external serial ports and JLINK debugging tools are used for fault analysis, then fault detection capability is improved, but device complexity and cost increase
Solution Approach 1:
The patent extracts the debugging functionality from external devices and integrates it into the SSD controller itself. The controller includes dedicated debugging modules and registers that allow fault information to be accessed through the existing PCIe interface, eliminating the need for external serial ports or JLINK tools while maintaining fault detection capability
Solution Approach 2:
The PCIe interface is made multi-functional by enabling it to serve both as a data transmission interface and a debugging interface. The controller uses the same PCIe configuration space and command sets to provide both normal operation and fault analysis functions, eliminating the need for separate external debugging hardware
2Device complexity
If external debugging interfaces are removed for safety and cost considerations, then device complexity is reduced, but fault analysis capability deteriorates
Solution Approach 1:
The patent introduces debugging registers within the PCIe configuration space as intermediaries between the host and the fault information. These registers act as a mediator that allows the host to access fault data through standard PCIe commands without requiring external debugging hardware, thus maintaining fault analysis capability while keeping the device simple
Solution Approach 2:
The SSD controller performs self-diagnosis and stores fault information in its own internal registers. The controller can autonomously detect faults, format the fault information, and make it accessible through the PCIe interface without requiring external debugging tools, enabling the device to service its own debugging needs
3Reliability
If vendor-specific commands are used for problem diagnosis, then fault information can be obtained, but the host cannot obtain useful log information when the device is lost
Solution Approach 1:
The patent makes the debugging function universal by implementing it through standard PCIe configuration space operations that work with any NVMe device. The host can use standard NVMe commands to access the debugging registers and retrieve fault information, making the solution adaptable to all devices without requiring device-specific command sets
Solution Approach 2:
The controller prepares debugging registers and fault information storage areas in advance during device initialization. The PCIe configuration space is pre-configured with debugging functionality, and the controller continuously monitors and stores fault information in these pre-prepared registers, so that fault data is immediately available when needed without requiring special preliminary actions
Data Source
AI summary
This application relates to the field of solid-state drive technology, and discloses a method for failure analysis of solid-state drive based on PCIe interface and a solid-state drive. The method comprises: writing, by a host, a command containing a predetermined flag to a first designated address in a solid-state drive; monitoring, by a controller of the solid-state drive, the first designated address to determine whether the first designated address has the predetermined flag; in response to the first designated address having the predetermined flag, writing, by the controller, fault information to a second designated address in batches and updating an offset address of corresponding content in a third designated address in the fault information with each write to the second designated address, and then clearing the content in the first designated address; reading, by the host, the second designated address and the third designated address, and writing the fault information in the second designated address to a designated position based on the offset address in the third designated address; and writing, by the controller, an end flag to the third designated address. When the NVMe device cannot be found on the host side, the fault information encountered by the customer can be obtained remotely to help analyze, locate and solve the problem.