PCIe SSD Link Quality Monitoring Through MAC Error Feedback
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Solution Overview
Problem
Hosts in computer systems cannot determine the link quality of a Peripheral Component Interconnect Express (PCIe) bus connecting them to solid-state storage devices until the signal quality deteriorates to the point of disconnection, leading to decreased user experience.
Innovation Solution
A memory controller with a PCIe media access control (MAC) layer, NVMe conversion circuit, flash memory control circuit, link quality monitoring circuit, and error counter circuit is used to monitor and report error count values to the host, enabling proactive link quality assessment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the host waits until signal quality deteriorates to the point of disconnection to detect and take actions, then the system structure remains simple, but the reliability of data transmission deteriorates
Solution Approach 1:
The patent implements a feedback mechanism where the memory controller continuously monitors PCIe link signal quality through error counting circuits that track transmission errors in both directions. Error count values are fed back to the host system through PCIe configuration space, enabling the host to detect deteriorating link quality and take proactive measures before disconnection occurs, thus improving data transmission reliability through continuous monitoring feedback
Solution Approach 2:
The memory controller performs self-monitoring of the PCIe link quality by internally counting transmission errors and automatically reporting error count values to the host through PCIe configuration space. This self-service approach allows the system to monitor its own health status without requiring additional external monitoring hardware, resolving the contradiction between reliability improvement and system complexity
2Reliability
If the host proactively monitors link quality through error count values, then the reliability of data transmission improves, but the device complexity increases
Solution Approach 1:
The patent makes the memory controller multi-functional by combining its existing data transmission control functions with additional link quality monitoring capabilities. The same PCIe interface and configuration space used for normal device communication are also utilized for error count reporting, allowing the host to proactively monitor link quality through existing universal interfaces without adding dedicated monitoring hardware, thus improving reliability while minimizing complexity increase
Data Source
AI summary
A method for monitoring link signal quality of a solid-state storage device is provided. The method includes the following steps: utilizing a PCIe media access control (MAC) layer to trigger an error notification signal in response to an error occurring on data transmission on a PCIe bus between a host and the solid-state storage device; utilizing a link quality monitoring circuit to transmit a first or second error count signal to an error counter circuit based on a transmission direction of the data transmission in response to the error notification signal; utilizing the error counter circuit to accumulate a first or second error count value based on the first or second error count signal; and utilizing the PCIe MAC layer to report the first or second error count value to the host through the PCIe bus in response to a configuration read packet from the host.