PCIe State Transition Time Adaptive Adjustment
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Solution Overview
Problem
In PCIe systems, inefficiencies in state transition times occur when devices rely on fixed delay times or patterns to wait for specific signals, leading to suboptimal performance.
Innovation Solution
A method for adaptively adjusting state transition times in PCIe systems by toggling clock request and reference clock signals based on training parameters, such as transition time, restoration delay, and latency tolerance report, to optimize state transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fixed delay time or same pattern is used for state transition, then device complexity is reduced, but productivity deteriorates due to suboptimal performance
Solution Approach 1:
The patent implements dynamic adjustment of state transition timing parameters (such as T_L0L1_REFCLK_ON, T_L0L1_REFCLK_OFF, T_L1L0_REFCLK_ON, T_L1L0_REFCLK_OFF) based on actual system conditions and training results, replacing fixed delay times with adaptive values that optimize performance for different operational scenarios
Solution Approach 2:
The system performs self-training through iterative measurement and adjustment of state transition parameters, where the PCIe device autonomously determines optimal timing values by monitoring signal conditions and adjusting parameters without external intervention, thereby improving productivity while maintaining manageable complexity
2Loss of time
If fixed delay time is used for signal waiting, then ease of operation is improved, but loss of time increases due to suboptimal waiting periods
Solution Approach 1:
The patent incorporates feedback mechanisms where the system measures actual signal assertion times, clock validation times, and circuit ready times during state transitions, then uses this feedback information to adjust timing parameters iteratively, minimizing waiting time while automating the optimization process
Solution Approach 2:
The system dynamically changes timing parameters (delay times, waiting periods) based on measured performance metrics and training results, optimizing the balance between ease of operation and time efficiency by adapting parameters to actual system behavior rather than using fixed conservative values
Data Source
AI summary
A method for adaptively adjusting state transition time in a Peripheral Component Interconnect (PCI) Express (PCIe) system and associated apparatus such as a root complex (RC) device and an endpoint device are provided. The method may include: toggling a clock request signal on a signal path coupled between the RC device and the endpoint device based on a request from the RC device or on a request from the endpoint device, wherein when the clock request signal toggles, the endpoint device transits from a first state to a second state; and toggling a reference clock signal from the RC device at a timing determined according to a training parameter among at least one predetermined parameter which is set dependent on at least one of the factors: a transition time, a restoration delay, a latency tolerance report (LTR) and a bias state, after the clock request signal toggles.