PCIe Storage Interface with Concurrent Request and Completion Engines
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Solution Overview
Problem
Current RAID storage systems face challenges in efficiently handling multiple PCIe storage devices with different communication standards, leading to performance bottlenecks and errors, as they require firmware processing for unsupported standards and stall completion processing when errors occur.
Innovation Solution
A RAID controller with PCIe device request and completion engines that operate concurrently to process I/O commands and notifications across various PCIe storage device communication standards, including NVMe, AHCI, and SCSI over PCIe, allowing hardware to handle completions for all supported standards without stalling other devices and masking errors to maintain performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a unified firmware processing approach is used for all PCIe storage device communication standards, then device compatibility is improved, but processing performance deteriorates due to firmware bottlenecks
Solution Approach 1:
The controller divides the processing function by device communication standard into separate hardware engines: an NVMe engine for NVMe devices, an AHCI engine for AHCI devices, and a SCSI engine for SCSI devices. Each engine is dedicated to processing commands for its specific standard, eliminating the firmware bottleneck while maintaining support for multiple standards through this segmented architecture.
2Reliability
If error processing stalls the entire completion processing pipeline, then error handling accuracy is improved, but system productivity deteriorates
Solution Approach 1:
The completion processing function is segmented by device standard into separate completion engines, each independent of others. When an error occurs in one engine (e.g., NVMe engine), only that specific engine stalls to handle the error, while other engines (AHCI, SCSI) continue processing completions for their respective devices without interruption.
Solution Approach 2:
Each completion engine has independent error handling capabilities tailored to its specific device standard. The NVMe completion engine handles NVMe-specific errors independently, the AHCI engine handles AHCI-specific errors independently, and so on. This localizes error impact to only the affected engine rather than stalling the entire system.
3Productivity
If concurrent hardware processing is implemented for multiple device standards, then processing performance is improved, but device complexity increases
Solution Approach 1:
Each hardware engine is designed with universal functionality to handle all completion types for its specific device standard. For example, the NVMe engine can handle all NVMe completion scenarios (success, error, timeout, interrupt), and the AHCI engine can handle all AHCI completion scenarios. This multi-functionality at the engine level reduces the need for additional specialized components, managing complexity while achieving concurrent processing.
Data Source
AI summary
Disclosed is a storage device interface. The storage device interface includes a plurality of PCIe device request engines. These PCIe device request engines receive I/O commands formatted for a respective one of a plurality of PCIe storage device communication standards. The storage device interface also includes a plurality of PCIe device completion engines. These PCIe device completion engines receive notifications of command completions from a plurality of PCIe storage devices that communicate using the aforementioned plurality of PCIe storage device communication standards. These notifications are validated. If an error is detected, processing of notifications of command completions associated with that device are blocked until the error is resolved. The plurality of PCIe device request engines and the PCIe device completion engines operate concurrently to process received I/O commands and received command completions.