PCIe Sub-Link Power Management via Latency Thresholds
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Solution Overview
Problem
Conventional PCIe power management systems fail to enable power-saving states for all sub-links due to constraints such as exit latency thresholds, leading to inefficient energy consumption, especially when multiple composite links share a common sub-link.
Innovation Solution
The processing circuitry determines which sub-links can support specific power-saving states without violating constraints by selectively enabling or disabling these states based on exit latency thresholds, allowing a subset of sub-links to enter power-saving modes while maintaining performance and bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional power management system is used, then power-saving states can be enabled, but some links remain unable to enter power-saving state due to exit latency constraints
Solution Approach 1:
The patent applies local quality by enabling power-saving states selectively for individual sub-links based on their specific characteristics and constraints. Instead of uniformly applying power management across all links, the system evaluates each sub-link's exit latency capabilities and enables power-saving states only where appropriate, allowing some sub-links to enter low-power states while others remain active to meet latency requirements.
Solution Approach 2:
The patent segments the PCIe link into multiple sub-links and applies independent power management control to each sub-link. This segmentation allows the system to differentiate between sub-links that can tolerate power-saving states and those that cannot, based on their specific latency requirements and operational characteristics.
2Use of energy by moving object
If power-saving states are enabled for all sub-links, then energy consumption is reduced, but exit latency thresholds are violated
Solution Approach 1:
The system applies local quality by making differentiated power management decisions for each sub-link. It evaluates the specific exit latency characteristics of each sub-link and enables power-saving states only for those sub-links where the exit latency remains within acceptable thresholds, while keeping other sub-links active to maintain timing requirements.
Solution Approach 2:
The patent applies partial action by enabling power-saving states for only a subset of sub-links rather than all sub-links. This partial application of power management allows the system to achieve energy savings on eligible sub-links while maintaining performance and latency compliance on sub-links where power-saving states would cause excessive exit latency.
3Use of energy by moving object
If selective power-saving state management is implemented, then more sub-links can enter power-saving state, but system complexity increases
Solution Approach 1:
The patent applies self-service by enabling sub-links to autonomously determine their own power-saving state eligibility based on their inherent characteristics and current operational context. Each sub-link essentially manages its own power state by evaluating whether entering a power-saving state would violate latency requirements, reducing the need for complex centralized control.
Solution Approach 2:
The system applies dynamics by making power management decisions that can change based on real-time conditions. The power-saving state enablement is not static but dynamically adjusted according to the operational status, latency requirements, and performance needs of each sub-link, allowing flexible adaptation to varying system conditions.
Data Source
AI summary
An apparatus is provided. The apparatus comprises interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions to determine that a first composite link of a plurality of composite PCIe links terminating at the same PCIe root port lacks support for enabling a desired power saving state or an exit latency for the first composite link is above a first latency threshold. The processing circuitry is further configured to determine whether an exit latency for a second composite link of the plurality of composite PCIe links is below a second latency threshold and selectively trigger at least one sub-link of the second composite link to enable the desired power saving state if the exit latency for the second composite link is below the second latency threshold.