PCI Express Switch Address Matching Using Segmented Limit Check

The patent segments the address matching process into two distinct phases: base address comparison and limit address verification. By dividing the single large comparison task into smaller sequential steps, the system avoids the need for a large number of simultaneous comparators. The base address register array is searched first to identify potential matches, then only the limit addresses of matching entries are verified against the target address range, significantly reducing the total comparator count needed.

The patent performs preliminary filtering by comparing the target address against base addresses first, before conducting the more resource-intensive limit address verification. This preliminary action eliminates non-matching entries early in the process, so that subsequent limit address comparisons are only performed on a small subset of potential matches, rather than all address registers simultaneously.

The patent implements periodic action by performing limit address verification only at specific intervals - specifically, only when a base address match is found. Instead of continuously verifying every base address comparison, the system periodically checks limit addresses only for matching entries, reducing the overall verification frequency while maintaining accuracy for valid matches.

The base address comparison serves as a preliminary filtering step that identifies which entries require subsequent limit address verification. This preliminary action ensures that limit address checking is performed only when necessary, maintaining validation accuracy while minimizing the total number of comparisons and reducing latency.

The patent segments the address validation function across different circuit components performed at different times: base address comparison is performed by one set of circuits, and limit address verification is performed by separate circuits only when needed. This temporal and functional segmentation allows the system to support more external devices without proportionally increasing the number of active comparators, thus reducing power consumption.

The patent applies partial action by performing complete limit address verification only for base address matches, rather than verifying all address registers simultaneously. This partial verification approach provides sufficient addressing accuracy for the number of supported devices without the excessive power consumption that would result from full simultaneous verification of all address registers.