PCIe Switch Control Architecture With Address Resolution Modules
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Solution Overview
Problem
Existing control systems for cloud data center switches face challenges in managing a large number of optical modules and hard disks, leading to increased design complexity, pin occupancy, and space requirements, as well as the need for complex control logic and specialized drivers.
Innovation Solution
A control system that uses a processor connected to a control module via a PCIe bus, with address resolution modules connected via address buses, allowing for reduced pin usage, simplified control logic, and eliminating the need for specialized drivers by using preconfigured address information to control execution devices like optical modules or hard disks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of optical modules or hard disks is increased to enhance network bandwidth and storage capacity, then the network bandwidth and storage capacity are improved, but the backplane design difficulty increases and the number of control signals increases
Solution Approach 1:
The patent introduces an address resolution module as an intermediary between the control module and execution devices. This module receives control instructions with address information from the control module, resolves the address to identify the target execution device, and then controls the corresponding device. This intermediary structure simplifies the backplane design by reducing the number of direct control signals needed from the control module.
Solution Approach 2:
The control system is segmented into distinct functional modules: a control module for issuing commands, an address resolution module for translating address information to device identifiers, and execution devices for performing operations. This segmentation allows each module to have a specialized function, reducing overall system complexity while enabling scalability.
2Speed
If a processor directly controls each port of an optical module via PCIe bus and FPGA, then the control is direct and responsive, but many FPGA pins are occupied and wire leads occupy large on-board space
Solution Approach 1:
The patent extracts the address resolution function from the FPGA control logic and implements it as a separate address resolution module. This extraction reduces the complexity and pin requirements of the FPGA while maintaining direct control capabilities. The address resolution module handles the translation of address information to device control signals, freeing up FPGA resources.
Solution Approach 2:
The address resolution module serves as an intermediary that receives control instructions from the control module and translates them into device-specific control signals. This intermediary approach reduces the number of wire leads needed on the backplane while maintaining efficient control response times.
3Adaptability or versatility
If a control module connects to multiple IO expansion modules via I2C bus, then the control logic is distributed, but the control logic becomes complex and requires specially developed drivers
Solution Approach 1:
The address resolution module is designed as a universal component that can handle different types of execution devices (optical modules, hard disks, etc.) through a standardized interface. The module receives control instructions with address information and automatically resolves them to the appropriate device, eliminating the need for device-specific control logic or specially developed drivers.
Solution Approach 2:
The system uses address information as a parameter to identify and control different execution devices. By changing the address parameter in control instructions, the same control module and address resolution module can control different devices without requiring changes to the control logic or specialized drivers for each device type.
Data Source
AI summary
A control system, a switch, and a method for controlling an execution device. The control system comprises a processor, a control module, and address resolution modules. The processor is connected to the control module by means of a peripheral component interconnection high-speed PCIe bus, the control module is connected to one or more address resolution modules by means of address buses, and each address resolution module is configured to be connected to one execution device, wherein address information of a port to be controlled on each execution device is preconfigured on the processor, and the address information is used for enabling the processor to address to a corresponding address resolution module by means of the control module. According to the control system, the number of occupied pins of the control module can be reduced, a specially developed driving program is not needed, the control logic is simple, and the operation is stable.