PCI Express Switch Base Address Sorting with Shift Vector
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Solution Overview
Problem
PCI Express switches face challenges in accommodating a large number of external devices due to the need for an exponentially increasing number of comparators and registers, leading to increased chip space and power consumption, as well as higher latency.
Innovation Solution
A novel method and device for reconfiguring base address registers in a switching device that supports rapid binary address searching, allowing for a large number of ports without the need for an exponentially increased number of comparators and registers, by using a shift vector to quickly and accurately insert new base addresses into an array while preserving the sorted order.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional switch architecture with simultaneous comparisons is used to accommodate more external devices, then the number of ports increases, but the number of comparators and registers increases exponentially
Solution Approach 1:
The patent segments the address comparison process into multiple phases. Instead of performing all comparisons simultaneously, it divides the 16 base address registers into groups and performs comparisons in sequential phases. This segmentation reduces the number of comparators needed at any one time from 256 to a manageable number, while still supporting 16 external devices.
Solution Approach 2:
The patent applies preliminary action by pre-sorting the base address registers in descending order before comparison. This preliminary arrangement allows the system to use a binary search approach, where comparisons are performed systematically from highest to lowest address. This pre-organization enables efficient address matching with fewer comparators and reduces the complexity of the comparison logic.
2Adaptability or versatility
If more comparators are implemented to support higher number of ports, then accommodation of external devices increases, but chip space consumption increases
Solution Approach 1:
The patent segments the comparison operation across multiple time phases rather than requiring all comparators to exist simultaneously. By dividing the 16 registers into groups and performing comparisons in sequential phases, the chip only needs to implement a small number of comparators that are reused across different phases, dramatically reducing the total chip area required.
Solution Approach 2:
The patent introduces dynamic time-multiplexing of comparators. The same physical comparators are dynamically allocated to different register groups in different phases. This dynamic reuse allows the system to support 16 ports with a fixed, small number of comparators, converting a static resource requirement into a dynamic, time-shared solution that minimizes chip space.
3Adaptability or versatility
If more comparators are implemented to support higher number of ports, then accommodation of external devices increases, but power consumption increases
Solution Approach 1:
The patent segments the comparison workload across multiple phases, activating only a small subset of comparators in each phase. This segmentation ensures that power consumption remains low and constant regardless of the total number of ports, as the same small number of comparators are reused rather than scaling up the comparator count with the number of ports.
Solution Approach 2:
The patent implements dynamic phase-based activation of comparators, where only the comparators needed for the current phase are active. This dynamic time-multiplexing approach maintains low power consumption by keeping the active comparator count constant, while the logical capacity to support more ports increases through temporal reuse of the same hardware resources.
4Adaptability or versatility
If more comparators are implemented to support higher number of ports, then accommodation of external devices increases, but system latency increases
Solution Approach 1:
The patent applies preliminary action by pre-sorting base address registers in descending order and organizing them into groups before the comparison process begins. This pre-organization enables a systematic binary search approach where the target address can be efficiently located by comparing with group boundaries first, then narrowing down within groups. This preliminary arrangement significantly reduces the number of comparison steps needed, thereby reducing latency despite using fewer comparators.
Solution Approach 2:
The patent segments the address space into groups of registers, allowing for hierarchical comparison. By first comparing with group boundary addresses and then with individual register addresses within the relevant group, the system reduces the total number of comparison iterations needed. This segmented approach maintains low latency by minimizing the depth of the comparison tree, even as the number of supported ports increases.
Data Source
AI summary
A base address sorting device in a switching device is disclosed that includes an array of base address registers in which each base address register contains a base address, an address shifting device; and a control logic element electrically coupled to the array of base address registers and operable, upon receiving a configuration command comprising a new base address, to implement a method for reconfiguring the contents of the array of base address registers. The method includes determining an insertion point base address register in the array of base address registers into which to write the new base address, shifting the contents of one or more base address registers array to other base address registers to preserve the sorted order, and shifting the contents of the configuration command into the insertion point base address register. The inserting results in preserving the pre-determined order of the register array content.