PCIe Switch Board Layout for Simplified Multi-Board Interconnection
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Solution Overview
Problem
The complexity and cost of building and maintaining converged data center architectures with multiple PCIe Switch processors in limited chassis space are high due to complex cable topologies and limited space, making it difficult to support flexible interconnection topologies and resource pooling systems.
Innovation Solution
A processor board design with specific internal and external connector configurations and circuits that allow for intersecting connections between processors, reducing cable complexity and enabling flexible interconnection topologies while maintaining signal quality and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple PCIe Switch processors are configured in one chassis to support huge PCIe resource demand, then the data processing capability and resource pooling capability are improved, but the device complexity and cable topology complexity increase significantly
Solution Approach 1:
The patent combines multiple PCIe Switch processors (first PCIe Switch processor and second PCIe Switch processor) onto a single processor board. This merging approach reduces the number of separate chassis and cable connections needed, thereby simplifying the cable topology while maintaining the ability to support huge PCIe resource demand through the integrated multi-processor configuration.
Solution Approach 2:
The processor board is designed with universal interconnection capabilities, where the first and second PCIe Switch processors can be interconnected through multiple pathways (first interconnection pathway, second interconnection pathway, third interconnection pathway). This multi-functional design allows the same board to support various interconnection topologies and PCIe resource configurations, reducing overall system complexity.
2Adaptability or versatility
If multiple PCIe Switch processors are configured in one chassis, then the resource pooling capability is improved, but the chassis space utilization becomes problematic due to limited space
Solution Approach 1:
The patent merges multiple PCIe Switch processors onto a single processor board, which significantly reduces the chassis space required compared to housing each processor in separate chassis. This consolidation maintains resource pooling capability while improving space utilization in the limited chassis environment.
Solution Approach 2:
The design embeds multiple PCIe Switch processors within a single processor board structure, creating a nested configuration where the first and second processors are housed within the same physical board. This nesting approach maximizes the use of available chassis space while maintaining the ability to pool PCIe resources effectively.
3Adaptability or versatility
If complex cable topologies are used to interconnect multiple PCIe Switch processors, then the interconnection flexibility is improved, but the construction and maintenance costs increase
Solution Approach 1:
The patent combines multiple interconnection pathways within a single processor board, eliminating the need for complex external cable topologies. The first, second, and third interconnection pathways are integrated directly on the board, reducing construction costs while maintaining interconnection flexibility for various PCIe configurations.
Solution Approach 2:
The processor board itself acts as an intermediary that provides multiple interconnection pathways between the first and second PCIe Switch processors. This eliminates the need for complex external cable assemblies and reduces maintenance costs, while still providing flexible interconnection options through the integrated pathways.
4Ease of manufacture
If processors are arranged with standard connector configurations, then the manufacturing simplicity is maintained, but the cable length and signal quality deteriorate
Solution Approach 1:
The patent implements local optimization of connector positions, placing the first and second connectors at specific locations on the processor board that are optimized for short interconnection distances. This local quality adjustment reduces cable length and improves signal quality without requiring changes to the overall manufacturing process or standard connector types.
Data Source
AI summary
The embodiments of the present disclosure provide a board and a server, which relates to the technical field of processor board card interconnection. By arranging the first internal connectors in the second internal connector configuration area and the second internal connectors in the first internal connector configuration area; the first processor is electrically connected to the first internal connectors through the first circuit, and the second processor is electrically connected to the second internal connectors through the second circuit, and the first circuit and the second circuit are arranged in an intersecting way. Based on the wiring design of the board of the embodiments of the present disclosure for multi-board interconnection, the complexity of the cable topology structure in the board group may be effectively simplified, thereby improving the maintenance efficiency of multi-card interconnection, and reducing the construction difficulty and maintenance cost.