PCIe Switch Addressing via Bus and Device ID Segmentation
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Solution Overview
Problem
Current PCIe technologies face limitations in efficiently managing large switch topologies due to the constraints of the bus:device.function number format, which restricts the number of available addresses and scalability in switching data between hosts and endpoints.
Innovation Solution
Implementing a PCIe-compliant switch with switching logic that utilizes unique combinations of bus numbers and device numbers to expand addressable combinations beyond the traditional 8-bit bus number field, allowing for 32 times more addresses and supporting larger networks by storing and switching data based on bus identifiers and device identifiers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the traditional 8-bit bus number field is used for addressing, then the PCIe switch can operate with simple addressing logic, but the number of available addresses is limited and scalability is restricted
Solution Approach 1:
The patent segments the addressing space by introducing a device number field to complement the existing bus number field. Instead of using a single 8-bit bus number that limits addressing capacity, the system divides the address identification into two separate components: bus number (5 bits) and device number (5 bits). This segmentation allows the PCIe switch to handle larger networks by combining these fields to uniquely identify endpoints, thereby improving scalability without requiring a complete redesign of the addressing logic.
Solution Approach 2:
The patent adds another dimension to the addressing space by introducing the device number field as a complementary identifier to the bus number field. This dimensional expansion transforms the addressing capability from a single-dimensional 8-bit bus number to a two-dimensional address space formed by the combination of bus number and device number fields, enabling significantly more addressable combinations and supporting larger PCIe networks.
2Quantity of substance
If the bus:device.function number format is used, then PCIe compatibility is maintained, but the number of addressable combinations is restricted
Solution Approach 1:
The patent merges the bus number field and device number field to create a combined addressing mechanism. By combining these two fields, the system generates a larger number of unique addressable combinations than either field could provide individually. This merging allows the PCIe switch to support a greater quantity of addressable endpoints while maintaining compatibility with the existing bus:device.function number format structure.
Solution Approach 2:
The patent enhances the universality of the addressing system by making the switch capable of handling both traditional bus number-only addressing and the new combined bus number-device number addressing. This multi-functionality allows the same PCIe switch infrastructure to support both smaller networks using traditional formatting and larger networks using the expanded addressing format, thereby increasing network size support without sacrificing backward compatibility.
Data Source
AI summary
One or more examples relate to an apparatus to switch data based on a bus identifier and a device identifier. Such an apparatus may include an upstream port for a respective peripheral component interconnect express (PCIe)-compliant communicative connection with a host; a downstream port for a respective PCIe-compliant communicative connection with an endpoint; and a switching logic. The switching logic may store a bus identifier and a device identifier for the endpoint; and switch data at least partially responsive to the bus identifier and the device identifier of the endpoint.