PCIe Switch Control Device Buffer Overflow Reset
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Solution Overview
Problem
In PCIe switch systems, abrupt link partner removal or power supply disconnection can cause the LTSSM to enter an abnormal state, leading to buffer overflow and CPU hang-ups due to the failure in informing the software layer of a link down, resulting in prolonged device restart times.
Innovation Solution
A control device comprising a first processor for data communication, a relay device for data transfer, and a third processor to detect buffer full states and halt conditions, with the third processor resetting the relay device to clear buffers and restore normal operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the LTSSM remains in an abnormal state without being returned to a normal state, then the PCIe switch continues to queue data in its buffer, but the buffer becomes full causing a blocking and CPU hang up
Solution Approach 1:
The patent implements a mechanism that performs preliminary detection of buffer full states and LTSSM abnormal states before they cause CPU hang up. The system proactively monitors buffer status and LTSSM state, and when abnormalities are detected, it automatically initiates a reset of the PCIe switch to prevent the CPU from entering a hang up state. This preliminary action prevents the problem from fully developing.
2Reliability
If a system reset is performed to restore normal operation, then the CPU hang up is resolved, but the device restart time is prolonged
Solution Approach 1:
The patent extracts the reset function from the CPU and implements it in a separate management entity or firmware layer. When a buffer full state or LTSSM abnormal state is detected, the system performs a targeted reset of only the PCIe switch or affected components rather than a complete system reset. This selective extraction of the reset function to a dedicated management layer reduces the restart time by avoiding unnecessary system-wide reset operations.
3Productivity
If the buffer continuously queues data without clearing, then data transmission is maintained, but the blocking occurs and CPU hang up is caused
Solution Approach 1:
The patent implements a feedback mechanism that continuously monitors buffer status and LTSSM state, and uses this information to control data transmission and trigger appropriate reset actions. When the buffer reaches a full state or when LTSSM enters an abnormal state, the feedback mechanism detects this condition and triggers a reset of the PCIe switch. This feedback loop ensures that data transmission continues normally under healthy conditions while automatically correcting abnormal states before they cause CPU hang up.
Data Source
AI summary
A control device includes a first processor, a relay device, a second processor, and a third processor. The first processor is configured to perform data communications with an electronic device. The relay device is configured to relay the data communications. The relay device includes a buffer for storing data to be transmitted or received in the data communications. The second processor is configured to check a state of the buffer to detect a buffer full state in which the buffer is full. The third processor is configured to check a state of the first processor to detect a halt state in which the first processor has halted. The third processor is configured to reset the relay device upon detecting the halt state and upon the second processor detecting the buffer full state.