PCIe Switch Link Power Control via DMA Descriptor Decoding
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Solution Overview
Problem
Current PCIe switch technologies struggle to meet the increasing demands of new and emerging applications for higher bandwidth and more connections, as the natural progression of increasing lanes and bandwidth through successive PCIe generations is insufficient.
Innovation Solution
A networking switch is designed with a descriptor decoder to decode DMA descriptor packets within transaction layer packets, and a link power controller to adjust the power state of links based on the descriptor data, optimizing power usage according to DMA operations and data sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the number of lanes and bandwidth are increased through successive PCIe generations, then the bandwidth and connection capacity are improved, but the power consumption increases and the solution becomes insufficient for new applications
Solution Approach 1:
The patent implements dynamic link power state adjustment based on actual traffic requirements. The link power controller monitors DMA descriptor packets and dynamically transitions links between active and low-power states, making the system adaptable to varying bandwidth demands rather than maintaining fixed high-bandwidth configurations that consume excessive power during low-utilization periods
Solution Approach 2:
The patent changes the power state parameter of PCIe links based on traffic analysis. By decoding DMA descriptor packets to determine data transfer requirements, the system adjusts link power states (e.g., L0, L1, L2, L3) to match actual bandwidth needs, thereby reducing power consumption while maintaining sufficient bandwidth performance
2Use of energy by moving object
If the link power state is reduced to save energy, then power consumption is decreased, but the bandwidth and performance may be affected
Solution Approach 1:
The patent employs feedback mechanisms where the link power controller continuously monitors DMA descriptor packet characteristics (data size, transfer patterns) and adjusts link power states accordingly. This closed-loop control ensures that bandwidth performance is maintained at levels appropriate for actual traffic demands while optimizing power consumption, preventing both over-provisioning and under-provisioning of link capacity
Solution Approach 2:
The patent performs preliminary decoding of DMA descriptor packets to predict future bandwidth requirements before making power state decisions. By analyzing the data payload and transfer characteristics in advance, the system can proactively adjust link power states to ensure sufficient bandwidth capacity is available when needed while minimizing power consumption during predictable low-utilization periods
Data Source
AI summary
A networking switch, including: a descriptor decoder configured to obtain descriptor data by decoding a direct memory access (DMA) descriptor packet encapsulated in a packet transferred, the packet from a host device; and a link power controller configured to adjust, based on the descriptor data, a power state of a link to be passed through in a bus interface connected to the networking switch.