Embedded PCIe Switch Erasure Coding for Scalable NVMe SSD Protection

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Solution Overview

Problem

Current NVMe-based Solid State Drives (SSDs) with RAID protection rely on external PCIe Add-In-Cards (AICs), which are costly and complex, limiting the adoption of NVMe SSDs in enterprise markets due to high costs, management complexity, and power consumption, and do not efficiently support large numbers of storage devices.

Innovation Solution

Implementing Erasure Coding within a Peripheral Component Interconnect Express (PCIe) switch using Field Programmable Gate Arrays (FPGAs) with integrated RAID controllers, allowing for embedded PCIe switches to manage multiple SSDs and co-processors, reducing the need for external AICs and optimizing data protection and management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If external PCIe Add-In-Cards (AICs) are used for RAID protection, then data protection capability is provided, but cost and device complexity increase significantly

Engineering Contradiction:

Improvedata protection capabilityVSAvoidsystem complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the RAID controller functionality directly into the PCIe switch chip, merging previously separate components (RAID controller + PCIe switch) into a single integrated device. This eliminates the need for external AICs and reduces system complexity while maintaining data protection capabilities through embedded erasure code engines.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The PCIe switch is designed to perform multiple functions: standard PCIe switching operations plus embedded RAID/erasure coding operations. This multi-functionality allows the same hardware component to provide both connectivity and data protection services, eliminating the need for dedicated external RAID controllers.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Quantity of substance

If multiple external AIC RAID controllers are deployed to support many SSDs, then storage capacity increases, but management complexity increases

Engineering Contradiction:

Improvenumber of SSDsVSAvoidmanagement complexity

Core Design Contradiction:

Quantity of substanceVSEase of operation

Solution Approach 1:

By integrating multiple erasure code engines within a single PCIe switch, the patent enables management of many SSDs through one unified controller rather than requiring multiple separate AICs. This consolidation simplifies management while supporting high storage capacity through the ability to connect numerous NVMe SSDs directly to the PCIe switch ports.

Inventive Principle:

Principle #5Merging (Combining)

3Reliability

If external AIC RAID controllers are used, then RAID functionality is provided, but power consumption increases

Engineering Contradiction:

ImproveRAID functionalityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent integrates RAID processing functionality directly into the PCIe switch, eliminating the need for separate powered AIC RAID controllers. The embedded erasure code engines perform RAID operations using the PCIe switch's existing processing resources, significantly reducing power consumption while maintaining full RAID functionality.

Inventive Principle:

Principle #5Merging (Combining)

4Reliability

If external AIC RAID controllers are deployed, then data protection is achieved, but cost increases

Engineering Contradiction:

Improvedata protectionVSAvoidcost

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent integrates erasure code engines directly into the PCIe switch fabric, eliminating the need for expensive external AIC RAID controllers. This integration provides the same data protection capabilities at a lower cost by utilizing the PCIe switch's existing processing and I/O resources rather than requiring separate dedicated hardware.

Inventive Principle:

Principle #5Merging (Combining)

5Quantity of substance

If CPU supports many PCIe lanes for multiple AICs, then connectivity to many devices is provided, but CPU cost and complexity increase

Engineering Contradiction:

Improvenumber of PCIe lanesVSAvoidCPU requirements

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS11860672B2Method for supporting erasure code data protection with embedded PCIE switch inside FPGA+SSD

Publication Date: 2024.01.02 SAMSUNG ELECTRONICS CO LTD

AI summary

A topology is disclosed. The topology may include at least one Non-Volatile Memory Express (NVMe) Solid State Drive (SSD), a Field Programmable Gate Array (FPGA) to implement one or more functions supporting the NVMe SSD, such as data acceleration, data deduplication, data integrity, data encryption, and data compression, and a Peripheral Component Interconnect Express (PCIe) switch. The PCIe switch may communicate with both the FPGA and the NVMe SSD.