Multi-Processor Network Architecture Using PCIe Switch Fabric
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Solution Overview
Problem
Conventional network switching devices face limitations in increasing performance due to power constraints and complexity, with multi-core processors not adequately addressing the need for significant performance enhancement while maintaining low power consumption and flexibility in handling high internet traffic.
Innovation Solution
A multi-processor network device architecture utilizing a PCI Express switching fabric to connect multiple processing cores, allowing for a scalable design that increases processor performance without raising operating frequencies, and distributes heat generation, enabling easy upgrades by replacing blades with new processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the operating frequency of microprocessors is increased to achieve higher performance, then network switching performance is improved, but power consumption increases beyond acceptable limits
Solution Approach 1:
The patent divides the processing system into multiple independent processing planes (first processing plane, second processing plane, third processing plane), each with its own processing cores. This segmentation allows the system to achieve high throughput by distributing work across multiple cores operating at moderate frequencies rather than relying on a single core at extremely high frequency, thus improving performance while controlling power consumption.
Solution Approach 2:
The patent transitions from a single-processor architecture to a multi-dimensional processing architecture with multiple processing planes connected through a switch fabric. This dimensional expansion enables parallel processing across multiple cores while maintaining manageable power consumption per core, achieving overall system performance improvement without proportional power consumption increase.
2Productivity
If multiple processing planes are added to increase processing capacity, then network switching performance is improved, but the system bus becomes overloaded
Solution Approach 1:
The patent introduces a dedicated switch fabric as an intermediary component that connects the multiple processing planes. This switch fabric acts as a mediator that manages communication between processing planes, eliminating the need for a single overloaded system bus. The switch fabric distributes traffic efficiently across multiple cores while maintaining manageable complexity through its specialized function of coordinating inter-plane communication.
3Device complexity
If processing cores are limited due to power and space constraints, then device complexity is reduced, but the ability to handle increased internet traffic is compromised
Solution Approach 1:
The patent segments the processing functionality across multiple independent processing planes, each containing processing cores. This segmentation enables the system to handle increased traffic by distributing packets across multiple cores in parallel, achieving high traffic handling capability without requiring a single overly complex processor. Each core operates at moderate complexity levels while collectively providing high throughput.
Solution Approach 2:
The patent implements multiple processing planes with redundant processing capacity. By providing more processing cores than a single-plane design would require, the system can handle peak traffic loads efficiently while maintaining low power consumption per core. The excess processing capacity is distributed across multiple planes, allowing the system to scale traffic handling capability without proportionally increasing complexity in any single plane.
Data Source
AI summary
A multi-processor architecture for a network device that includes a plurality of barrel cards, each including: a plurality of processors, a PCIe switch coupled to each of the plurality of processors, and packet processing logic coupled to the PCIe switch. The PCIe switch on each barrel card provides high speed flexible data paths for the transmission of incoming/outgoing packets to/from the processors on the barrel card. An external PCIe switch is commonly coupled to the PCIe switches on the barrel cards, as well as to a management processor, thereby providing high speed connections between processors on separate barrel cards, and between the management processor and the processors on the barrel cards.