PCIe Switch Flag Control for Independent Peripheral Power Modes
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Solution Overview
Problem
Existing PCIe bus technologies require all peripheral components to enter and exit low power consumption modes simultaneously, leading to inefficient power saving and excessive power consumption.
Innovation Solution
A computer system with a switch and flag registers allows individual peripheral components to enter and exit low power consumption modes independently by setting low power consumption and wake-up flag bits, using a processor and controllers to manage power and clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If all peripheral components under a PCIe switch enter low power consumption mode simultaneously, then the system can achieve power saving, but the power saving efficiency is poor and power consumption is excessive
Solution Approach 1:
The patent segments the power management control by introducing individual flag registers for each peripheral component. Instead of controlling all components uniformly, each component can independently set its own low power consumption flag, enabling selective and independent power management for each peripheral device under the PCIe switch.
Solution Approach 2:
The patent implements dynamic power management by allowing peripheral components to independently enter and exit low power consumption modes based on their actual operational needs. The flag register mechanism enables flexible, real-time adjustment of power states without requiring all components to synchronize their power transitions.
2Device complexity
If all peripheral components enter and exit low power consumption mode simultaneously, then the control mechanism is simple, but the power saving effect is insufficient
Solution Approach 1:
The patent divides the control mechanism into individual flag registers for each peripheral component, allowing independent power state management. This segmentation increases control complexity slightly but dramatically improves power saving effectiveness by enabling selective power management.
Solution Approach 2:
The patent applies local quality control by giving each peripheral component its own power management flag register. This allows each component to have customized power state control based on its specific operational requirements, rather than applying uniform power management across all components.
3Device complexity
If peripheral components cannot individually enter low power consumption mode, then the system structure is simple, but power consumption cannot be optimized
Solution Approach 1:
The patent introduces individual flag registers for each peripheral component, segmenting the power management control. This segmentation adds structural complexity but enables fine-grained power optimization by allowing each component to independently control its power state.
Solution Approach 2:
The patent changes the control parameter from a unified power state flag to individual component-specific flags. This parameter change enables precise control over each peripheral component's power state, allowing optimization based on individual component needs rather than collective behavior.
Data Source
AI summary
A computer system and a mode switching method thereof are provided. The computer system includes a processor, a plurality of peripheral components, and a switch. The switch is coupled to the processor via a first transmission interface link and respectively coupled to the plurality of peripheral components via second transmission interface links. The switch includes a first flag register and a second flag register. When a first target peripheral component in the peripheral components is to be entered into a low power consumption mode, the processor sets a low power consumption flag bit corresponding to the first target peripheral component in the first flag register. When a second target peripheral component in the low power consumption mode in the peripheral components transmits a wake-up signal to the switch, the switch sets a wake-up flag bit corresponding to the second target peripheral component in the second flag register.