PCIe Switch Host Interface Latency Reduction
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Solution Overview
Problem
As networks grow larger and more complex, they experience delays and require more physical hardware, leading to increased costs and space usage, with existing PCIe interconnect configurations still suffering from bottlenecks and inefficiencies.
Innovation Solution
The implementation of a PCIe link directly connecting a host to a switch, where packet conversion and routing occur, allowing the removal of HBA or NIC hardware from the host and integrating their functions into the switch ASIC, enabling reduced latency, increased compute density, and simplified protocol handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If HBA or NIC hardware is retained in the host, then protocol conversion functionality is available, but device complexity and space usage increase
Solution Approach 1:
The patent extracts the protocol conversion functionality from the host's HBA or NIC hardware and relocates it to the switch's ASIC. This removes the need for complex host-side network interface cards while maintaining protocol conversion capabilities at the switch, directly resolving the contradiction by reducing host device complexity without sacrificing adaptability.
Solution Approach 2:
The patent merges the protocol conversion functionality into the switch's ASIC, combining multiple functions (packet reception, protocol conversion, and routing) into a single integrated component. This consolidation eliminates the need for separate HBA or NIC hardware in the host, reducing device complexity while preserving protocol conversion versatility.
2Productivity
If PCIe links are extended to connect host to switch, then compute density increases, but signal integrity deteriorates requiring retimers
Solution Approach 1:
The patent introduces retimer devices as intermediary components between the host and switch to maintain signal integrity over extended PCIe links. The retimers actively regenerate and condition the PCIe signals, allowing the links to span greater distances without compromising reliability, thus enabling higher compute density while maintaining signal quality.
3Adaptability or versatility
If multiple protocol support is implemented in host adapters, then adaptability increases, but device complexity and cost increase
Solution Approach 1:
The patent implements multi-protocol support in the switch's ASIC rather than in individual host adapters. The universal switch can handle multiple protocols (FC, Ethernet, InfiniBand, etc.) and perform protocol conversion centrally, allowing simple host adapters to communicate with the switch without requiring complex multi-protocol capabilities in each adapter.
Solution Approach 2:
The patent extracts protocol handling complexity from the host adapters and relocates it to the switch. This allows host adapters to be simplified while the switch assumes the burden of multi-protocol support and conversion, resolving the contradiction by maintaining adaptability at the network level rather than at each host interface.
Data Source
AI summary
A host connected to a switch using a PCI Express (PCIe) link. At the switch, the packets are received and routed as appropriate and provided to a conventional switch network port for egress. The conventional networking hardware on the host is substantially moved to the port at the switch, with various software portions retained as a driver on the host. This saves cost and space and reduces latency significantly. As networking protocols have multiple threads or flows, these flows can correlate to PCIe queues, easing QoS handling. The data provided over the PCIe link is essentially just the payload of the packet, so sending the packet from the switch as a different protocol just requires doing the protocol specific wrapping. In some embodiments, this use of different protocols can be done dynamically, allowing the bandwidth of the PCIe link to be shared between various protocols.