PCIe Switch Dynamic Lane Routing for Multi-Node NVMe Access
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Solution Overview
Problem
Current PCIe architectures do not enable multiple endpoints to access a single NVMe SSD simultaneously, limiting the potential for high-performance data transmission and multi-path data access in non-volatile memory express systems.
Innovation Solution
A system and method that includes a switch module capable of switching between single node and multi-node PCIe transmission modes by selectively coupling and routing lanes between computing device interfaces and NVMe SSDs, using multiplexers to enable or disable lanes based on control signals, allowing for flexible lane configurations that optimize data transmission paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If PCIe uses point-to-point topology with single node mode, then transmission speed and reliability are improved, but multi-access capability and system versatility are limited
Solution Approach 1:
The PCIe switch enables dynamic topology transformation, allowing the system to switch between point-to-point single-node mode and multi-node mode. The switch module can dynamically configure lane assignments and connection paths based on operational requirements, providing adaptability while maintaining high-speed transmission capabilities in different operational contexts
Solution Approach 2:
The PCIe switch serves multiple functions: it acts as a simple pass-through in single-node mode for maximum speed, and as a multi-path router in multi-node mode for enhanced versatility. This universal component handles both transmission speed optimization and multi-access coordination, eliminating the need for separate dedicated hardware for each mode
2Adaptability or versatility
If PCIe switch enables multiple endpoints access to single endpoint, then adaptability and multi-path access are improved, but transmission speed and performance are reduced
Solution Approach 1:
The PCIe switch segments the data transmission paths by dividing the available lanes into separate virtual channels for different endpoint pairs. Each endpoint pair can utilize dedicated lane segments during their active communication period, ensuring full bandwidth utilization and maintaining high transmission speeds even when multiple endpoints are connected to the same NVMe SSD
Solution Approach 2:
The switch implements time-division multiplexing where different endpoint pairs are granted access to the NVMe SSD in periodic time slots. During each slot, a specific endpoint pair receives dedicated lane allocation and can transmit data at full speed without interference from other endpoints, thus maintaining high transmission performance while enabling multi-access capability
3Adaptability or versatility
If PCIe uses shared parallel bus architecture, then multi-access capability is improved, but transmission speed and performance scaling are reduced
Solution Approach 1:
The invention transitions from the traditional two-dimensional shared bus architecture to a multi-dimensional point-to-point mesh topology enabled by the PCIe switch. Data can travel through multiple dimensional paths (different lane combinations and routing options) between endpoints, providing both multi-access capability and high-speed transmission by exploiting the additional spatial dimensions created by the switch fabric
Data Source
AI summary
A system for switching between a high performance mode and dual path mode is disclosed. The system includes a first device, a second device, a third device, and a switch configured to receive control signals, and in response causing the switch to selectively couple one or more first lanes of the first device or one or more second lanes of the second device to third lanes of the third device to yield enabled lanes. The system also include a number of the enabled lanes is less than or equal to a number of the third lanes, and the switch is configured to route the enabled lanes associated with the first device to a first portion of the third lanes in an increasing order and to route the enabled lanes associated with the second device to a second portion of the third lanes in a decreasing order.