PCIe Switch MSI Scheduling for IOPS Efficiency

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Solution Overview

Problem

PCIe switches experience delays in handling input/output requests due to large amounts of pending works, leading to reduced input/output operations per second (IOPS) efficiency in computer systems.

Innovation Solution

A scheduling method for PCIe switches that determines a scheduling sequence for message signal interrupts (MSIs) and read/write requests based on the amount of MSIs, ensuring they are handled in a first-in-first-out order to prevent delays and improve IOPS efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the PCIe switch handles a large amount of input/output requests to multiple electronic devices, then the data access capacity is improved, but the handling of finished input/output requests corresponding to MSIs is delayed

Engineering Contradiction:

Improveamount of input/output requestsVSAvoiddelay in handling MSIs

Core Design Contradiction:

Quantity of substanceVSLoss of time

Solution Approach 1:

The patent segments the handling process into two distinct queues: a first queue for MSIs and a second queue for read/write requests. This segmentation allows independent management and scheduling of different request types, preventing MSI handling from being blocked by the volume of read/write requests, thus resolving the delay issue while maintaining high data access capacity

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic scheduling by adjusting the number of threads allocated to handle MSIs based on the amount of pending MSI requests. When MSI amount exceeds a threshold, additional threads are allocated to MSI handling, creating a dynamic response to workload conditions that prevents delays while maintaining system efficiency

Inventive Principle:

Principle #15Dynamics

2Productivity

If the PCIe switch processes read/write requests first, then the data access throughput is improved, but the MSI notification to the host is delayed

Engineering Contradiction:

Improvedata access throughputVSAvoidnotification delay

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent divides the request processing into separate queues and thread groups: one dedicated to MSIs and another to read/write requests. This ensures that read/write requests can be processed in bulk for high throughput while MSI notifications are handled independently and transmitted to the host without delay, even when read/write request volume is high

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements preliminary action by allocating specific threads to handle MSIs in advance and ensuring they are ready to process MSI requests immediately when they arrive. This preliminary preparation ensures that MSI notifications can be transmitted to the host without delay, even while read/write requests are being processed in the background

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS10628358B2Scheduling method, PCIe switch and electronic system using the same

Publication Date: 2020.04.21 WIWYNN CORP

AI summary

The present invention provides a scheduling method for a peripheral component interconnect express (PCIe) switch of an electronic system. The PCIe switch is utilized for handling input/output requests of a host of the electronic system. The scheduling method includes the PCIe switch determining a scheduling sequence of message signal interrupts (MSIs) and read/write requests corresponding to the input/output requests according to amount of the message signal interrupts corresponding to the input/output requests; and the PCIe switch handling the message signal interrupts and the read/write requests according to the scheduling sequence.