PCIe Switch Architecture for Direct NVMe-FPGA Data Access
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Solution Overview
Problem
The architecture of existing access acceleration systems for storage devices leads to a central processing unit (CPU) operating at full load, resulting in poor efficiency in system data processing due to direct CPU involvement in data transmission and processing.
Innovation Solution
An access acceleration system that enables point-to-point data transmission between computing chips, such as FPGAs, and storage devices like NVMe SSDs, utilizing a storage accelerate architecture (SAA) to achieve direct memory access (DMA) functions, allowing hardware subsystems to independently read and write memory without CPU intervention, thereby reducing CPU load and enabling additional PCIe devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the CPU is directly connected to storage devices and PCIe devices through root complex, then data transmission can be achieved, but the CPU operates at full load resulting in poor data processing efficiency
Solution Approach 1:
The patent introduces a PCIe switch as an intermediary device between the CPU root complex and multiple PCIe devices (storage devices and computing chips). The PCIe switch handles data routing and transmission tasks, freeing the CPU from direct involvement in data I/O operations. This mediator architecture allows the CPU to focus on computation while the PCIe switch manages data flow, thereby improving data processing efficiency without significantly increasing system complexity.
2Power
If the CPU handles all data reading and allocation for FPGA processing, then data transmission is possible, but the CPU frequently operates at full load
Solution Approach 1:
The patent extracts the data I/O handling function from the CPU by introducing a PCIe switch. The PCIe switch takes over the tasks of data reading, buffering, and allocation to FPGA devices, removing this burden from the CPU. This extraction allows the CPU to operate at lower power consumption levels while the PCIe switch efficiently manages data transmission, thereby improving overall system data processing efficiency without increasing CPU load.
3Adaptability or versatility
If multiple storage devices and PCIe devices are connected through root complex, then device connectivity is achieved, but the CPU cannot handle the workload efficiently
Solution Approach 1:
The patent segments the PCIe device connection architecture by introducing a PCIe switch that can independently manage multiple storage devices and computing chips. Instead of all devices competing for CPU attention through the root complex, the PCIe switch creates separate management domains for different device types. This segmentation allows the system to support more PCIe devices (improving adaptability) while the CPU only needs to manage high-level resource allocation, making load management much easier.
Data Source
AI summary
Embodiments of the present disclosure provide an access acceleration system for storage devices. The system comprising: a central processing unit, a Peripheral Component Interconnect Express (PCIe) device, a storage device, a computing chip and memories, wherein: the PCIe device comprises a root complex device, a PCIe switch, and a PCIe endpoint; the central processing unit is in communication connection with an upstream port of the PCIe switch through the root complex device, the storage device is in communication connection with a downstream port of the PCIe switch, the computing chip is in communication connection with a downstream port of the PCIe switch through the PCIe endpoint, and the storage device and the computing chip are in communication connection with different downstream ports of the PCIe switch, respectively; and the central processing unit and the computing chip are electrically connected to different one of the memories.