PCIe Switch P2P Transfers for SSD Test Time Reduction
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Solution Overview
Problem
The existing data comparison test methods for solid state drive (SSD) devices are bottlenecked by the bandwidth limitations of the host memory and interface protocols, leading to prolonged test times and inefficiencies in testing multiple SSD devices.
Innovation Solution
A memory device test apparatus and method utilizing peer-to-peer transfers between PCIe endpoints, where a comparison test unit connected to a PCIe switch performs writing, reading-back, and comparison processes without relying on the host memory, using field programmable gate array (FPGA) devices as PCIe endpoints to manage data flows and comparisons directly between SSD devices and the test unit, thereby bypassing upstream bandwidth constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If data comparison test uses host memory and interface protocols, then test coverage is comprehensive, but test time is prolonged due to bandwidth limitations
Solution Approach 1:
The patent introduces a PCIe switch as an intermediary device between the host subsystem and multiple SSD devices. The PCIe switch enables peer-to-peer transfers that bypass the host memory bandwidth bottleneck, allowing direct data movement between SSDs and test units through the PCIe fabric. This mediator architecture resolves the contradiction by providing a high-bandwidth path that doesn't depend on host memory capacity.
Solution Approach 2:
The test architecture is segmented into independent testing channels, each with its own comparison test unit and PCIe endpoint. Multiple SSD devices can be tested simultaneously in parallel through the PCIe switch, dividing the overall testing workload into concurrent segments. This segmentation eliminates the sequential bottleneck and improves overall testing productivity without sacrificing test coverage.
2Productivity
If multiple SSD devices are connected to PCIe switches, then concurrent testing capability is improved, but host memory bandwidth bottleneck is worsened
Solution Approach 1:
The PCIe switch acts as a mediator that manages multiple SSD connections without requiring the host subsystem to handle all the complexity. The switch provides virtualization and routing capabilities that enable multiple concurrent test channels while isolating the host from the complexity of managing multiple high-speed devices simultaneously.
Solution Approach 2:
The patent moves the data transfer path from the traditional host memory dimension to the PCIe fabric dimension. By utilizing the PCIe switch's routing capabilities and peer-to-peer transfer mechanism, the system adds a new dimensional path for data movement that is independent of host memory bandwidth constraints, enabling scalable concurrent testing.
3Productivity
If peer-to-peer transfers are used between PCIe endpoints, then bandwidth bottleneck is eliminated, but system architecture complexity is increased
Solution Approach 1:
The PCIe switch provides universal functionality that handles both traditional host-mediated transfers and peer-to-peer transfers. The same PCIe fabric and switch infrastructure support multiple communication patterns, eliminating the need for separate dedicated pathways. This multi-functionality reduces architecture complexity while enabling high-speed peer-to-peer data transfer.
Solution Approach 2:
The comparison test units and SSD devices perform self-service data transfers through peer-to-peer PCIe transactions without requiring host memory involvement. The test units autonomously generate test patterns, initiate transfers, and receive data directly from SSDs through the PCIe fabric, eliminating the need for host memory as an intermediary and simplifying the data path.
Data Source
AI summary
Disclosed herein are a method and an apparatus for shortening a data comparison test time by using peer-to-peer transfers between peripheral component interconnect express (PCIe) endpoints when testing solid state drive (SSD) devices. A memory device test apparatus performing a data comparison test of a memory device mounted in a downstream port of a peripheral component interconnect express (PCIe) switch by performing a writing process and a reading-back process by a control of a host central processing unit (CPU) includes: a comparison test unit (FPGA) connected to the downstream port of the PCIe switch, performing peer-to-peer communication with the memory device to supply write data to the memory device and receive read-back data from the memory device, and performing the data comparison test.