PCIe Switch Routing Control Using System Port Address Translation
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Solution Overview
Problem
The existing routing control methods for PCIe switches face a shortage of bus numbers, particularly in large-scale data centers and highly reliable computer systems, due to the finite nature of bus numbers required for physical topology matching, limiting the number of devices that can be connected.
Innovation Solution
The proposed solution involves using a system port address (SPA) to route packets between PCIe switches, allowing for the conversion of destination bus numbers into SPAs and assigning unique SPAs to external ports, enabling flexible routing that minimizes the need for bus number assignment based on physical topology, thereby increasing the number of devices that can be connected beyond the traditional 256-device limit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bus numbers are assigned according to physical topology in PCIe switches, then routing can be performed correctly, but the number of available bus numbers is limited to 256, which restricts the number of connectable devices
Solution Approach 1:
The patent introduces a translation mechanism that acts as an intermediary between the physical bus number space and the logical device address space. The translation table in the PCIe switch converts physical bus numbers to logical addresses, allowing the system to maintain correct topology-based routing while providing a larger logical address space that is not constrained by the 256 bus number limit. This intermediary translation layer decouples the routing function from the address assignment function.
Solution Approach 2:
The patent changes the parameter space by introducing logical addresses that are distinct from physical bus numbers. While bus numbers remain constrained to 256 values for routing purposes, the system now uses a separate logical address space that can accommodate more than 256 devices. This parameter separation allows the system to maintain the original bus number constraints for routing while expanding the addressable device space.
2Adaptability or versatility
If a large number of PCIe switches are deployed to connect many devices, then device connectivity increases, but the consumption of bus numbers in unintended places (within switches and between switches) exacerbates the shortage
Solution Approach 1:
The patent extracts the address translation function from the bus number assignment process. By separating the routing function (which uses bus numbers) from the device identification function (which uses logical addresses), the system can expand device connectivity without proportionally increasing bus number consumption. The translation table extracts and manages the mapping relationship, allowing bus numbers to be reused across different switch contexts.
Solution Approach 2:
The translation table mechanism serves multiple functions: it maintains routing correctness based on physical topology, provides expanded logical addressing for more devices, and enables bus number reuse across different parts of the network. This multi-functional approach allows a single mechanism to address connectivity needs without linearly increasing bus number consumption.
3Ease of operation
If bus numbers are freely assigned for routing, then routing flexibility increases, but the finite nature of bus numbers (limited to 256) creates a shortage in large-scale systems
Solution Approach 1:
The patent segments the addressing function into two distinct parts: bus numbers for routing segmentation and logical addresses for device identification. The bus number space is segmented into 256 values for routing purposes, while the logical address space is segmented to accommodate more than 256 devices. This segmentation allows each part to operate independently within its constraints, maintaining routing flexibility while enabling larger system scale.
Data Source
AI summary
The present invention eliminates the shortage of bus numbers in routing control using PCIe switches. A system port address (SPA) is associated with a destination bus number and is assigned to a port (external port) connected to a server and a device. When packets sent from the server or the device are received at the external port, the system port address (SPA) corresponding to the destination bus number having the packets is determined, and the SPA is added to the packets as a label. This SPA is used to route the packets sent between ports (internal ports) that connect switches. When the packets arrive at the external port to which the target server or device is connected, the destination bus number having packets is used to send the packets to the server or device connected to the external port.