PCI Express Switch with Local SRAM and Encryption
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Solution Overview
Problem
Current systems face challenges in connecting multiple radio devices to a host with low latencies due to throughput limitations of the PCI bus and contention issues with shared host memory, particularly in low-power, small form factor systems, which hinder performance enhancements like packet encryption and QoS support.
Innovation Solution
A scalable PCI Express switch with a memory interface and optional packet encryption engine, allowing for independent connections to each radio device, storing packets in high-speed SRAM to reduce latency and contention, and using a hardware-based encryption engine for efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If packets are stored in host memory, then memory space is shared among multiple devices, but latency increases due to contention for host memory and PCI Express interface
Solution Approach 1:
The patent divides the memory storage function into separate segments: host memory for general purposes and switch-local memory for packet buffering. This segmentation eliminates contention for host memory by providing dedicated packet storage at the switch, reducing fetch latency while maintaining memory space efficiency through proper allocation.
Solution Approach 2:
The switch acts as an intermediary between host memory and radio devices. It buffers packets in its local memory and manages DMA transfers, mediating the data flow to eliminate direct contention for host memory and PCI Express interface, thereby reducing latency without sacrificing memory sharing capabilities.
2Adaptability or versatility
If a standard PCI Express switch is used, then multiple radios can be connected, but cost increases and performance enhancements are limited
Solution Approach 1:
The patent implements a multi-functional switch that combines standard PCI Express switching with additional capabilities: packet buffering in local memory, hardware encryption/decryption engines, and priority-based arbitration. This universal design provides multi-radio connection capability while adding performance enhancements at lower cost than specialized high-end switches.
Solution Approach 2:
The switch allows dynamic configuration of performance parameters including buffer sizes, encryption keys, and priority levels for different radio devices. This parameter flexibility enables the same hardware to adapt to different performance requirements without increasing base cost or complexity.
3Reliability
If packet encryption is performed offline in the MAC, then encryption can be hardware assisted, but processing time increases linearly with packet size
Solution Approach 1:
The switch performs packet encryption as a preliminary action before packets reach the radio MAC. By encrypting packets in advance at the switch level, the system eliminates the linear time penalty of offline MAC-based encryption while maintaining security. The hardware encryption engine processes packets efficiently before they are transmitted.
4Productivity
If multiple parallel PCI busses or wider/faster PCI bus are used, then throughput increases, but power consumption and space requirements increase
Solution Approach 1:
The patent replaces the traditional mechanical PCI bus architecture with a PCI Express-based system that uses point-to-point serial connections instead of parallel buses. This substitution achieves higher throughput with lower power consumption and smaller form factor, eliminating the need for multiple parallel busses or wider/faster PCI connections.
Data Source
AI summary
A switching interface comprising a switch having an input and a plurality of outputs, and a memory associated with the switch. The switch is adapted to receive a packet from the input, the packet to be forwarded to a destination device coupled to a one of the plurality of outputs. The switch is responsive to store the packet in the associated memory. The switch is further responsive to a signal from the destination device to forward the packet from the associated memory to the destination device through the one of the plurality of outputs. Optionally, the switching interface may further comprise a packet encryption engine coupled between the input and the associated memory. Typically, the output devices coupled to the plurality of outputs will each have its own separate encryption process; in these scenarios the encryption engine will have logic for determining the appropriate encryption for the output device.