PCIe Switch Systolic Array for AI Data Routing
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Solution Overview
Problem
Conventional PCIe switches are inefficient in handling the increasing demands of robust communication required for advanced AI learning and data analytics, as they primarily rely on switching transaction layer packets based on address or requirement identifiers without advanced analysis capabilities.
Innovation Solution
A PCIe switch architecture incorporating a data and control path systolic array that receives transaction layer packets, determines their nature through programmable filters, and analyzes them within a systolic array for intelligent routing to destination ports, enabling real-time data analysis and AI learning applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional PCIe switching techniques are used to switch transaction layer packets based on address or requirement identifier, then the switching function is simple and device complexity is low, but communication efficiency is insufficient for advanced AI learning and data analytics
Solution Approach 1:
The PCIe switch is segmented into multiple functional units including a systolic array for parallel packet analysis, programmable filters for classification, and multiple destination ports. This segmentation allows the switch to handle complex AI learning and data analytics traffic by distributing processing tasks across specialized units, thereby improving communication efficiency without overwhelming a single processing component.
Solution Approach 2:
The patent implements dynamic routing capabilities where the switch can adaptively route transaction layer packets based on real-time analysis by the systolic array and programmable filters. This dynamic behavior allows the system to optimize communication paths for different types of traffic (e.g., AI learning vs. data analytics), improving overall communication efficiency while maintaining manageable device complexity through software-configurable rules.
2Adaptability or versatility
If traditional PCIe switch architecture is used, then device complexity is low and ease of manufacture is good, but advanced applications such as AI learning and data analytics cannot be supported without CPU intervention
Solution Approach 1:
The PCIe switch incorporates a systolic array and programmable filters that enable the device to autonomously analyze and route transaction layer packets for advanced applications like AI learning and data analytics. This self-service capability eliminates the need for CPU intervention in these operations, allowing the switch to handle complex workloads independently while maintaining adaptability to different application requirements.
Solution Approach 2:
The patent designs the PCIe switch with multi-functional capabilities by integrating a systolic array that can be configured for different analysis tasks, programmable filters that can classify various packet types, and multiple destination ports that support diverse applications. This universal design allows a single device to support both traditional switching functions and advanced AI learning/data analytics applications, improving adaptability without proportionally increasing device complexity.
3Adaptability or versatility
If PCIe switch creates multiple endpoints out of one endpoint to allow sharing, then endpoint sharing capability is improved, but routing complexity and device complexity increase
Solution Approach 1:
The systolic array acts as an intermediary processing unit that receives transaction layer packets, performs parallel analysis to determine packet nature and destination requirements, and then routes packets to appropriate destination ports. This intermediary structure simplifies routing complexity by centralizing the decision-making process in a specialized unit rather than distributing complex routing logic across multiple endpoints, thereby maintaining manageable device complexity while improving endpoint sharing capability.
Data Source
AI summary
The present subject disclosure provides a switch architecture with data and control path systolic array that can be used for real time data analysis or Artificial Intelligence (AI) learning. A systolic array is described which analyzes the TLPs received by an uplink port and processes the TLPs according to pre-programmed rules. Then the TLP is forwarded to a destination port. The reverse operation is described as well.