PCIe Device Throughput Analysis for QOS Control
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Solution Overview
Problem
Existing PCIe interface devices struggle to provide uniform Quality of Service (QOS) across multiple functions and lack effective buffer control performance, leading to inefficiencies in data transmission and processing.
Innovation Solution
A PCIe interface device equipped with a performance analyzer and a traffic class controller to measure throughputs of multiple functions and dynamically allocate traffic class values to transaction layer packets, as well as a buffer controller to manage buffer storage and output ordering based on transaction layer packet IDs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a PCIe interface device supports multiple functions with different throughput requirements, then the device can handle diverse data transmission needs, but it becomes difficult to provide uniform Quality of Service (QOS) across all functions
Solution Approach 1:
The patent applies local quality by measuring and monitoring throughput characteristics specific to each function individually, then assigning traffic class values tailored to each function's actual performance. This allows the system to provide uniform QOS appearance while accommodating diverse throughput requirements of different functions through localized measurement and differentiation.
2Reliability
If the device dynamically allocates traffic class values based on measured throughput, then QOS uniformity improves, but device complexity increases due to additional measurement and control components
Solution Approach 1:
The system performs self-measurement of throughput for each function using built-in counters and monitors, then automatically assigns traffic class values without requiring external intervention. The performance analyzer and traffic class controller work autonomously to measure, compare, and allocate traffic classes, reducing the need for complex external management systems.
3Reliability
If buffer storage capacity is increased to handle peak data transmission, then data loss decreases, but buffer management complexity and potential bottlenecks increase
Solution Approach 1:
The patent implements dynamic buffer management where the buffer controller actively monitors buffer status and flow control signals, dynamically adjusting data transmission based on real-time conditions. When the buffer is full or flow control indicates congestion, the system dynamically pauses or prioritizes transmissions, providing stable data loss prevention without requiring excessive buffer capacity.
Data Source
AI summary
Provided are a Peripheral Component Interconnect Express (PCIe) device and a method of operating the same. The PCIe device may include a performance analyzer, a delay time information generator and a command fetcher. The performance analyzer may measure throughputs of a plurality of functions, and generate throughput analysis information indicating a comparison result between the throughputs of the plurality of functions and throughput limits corresponding to the plurality of functions. The delay time information generator may generate a delay time for delaying a command fetch operation for each of the plurality of functions based on the throughput analysis information. The command fetcher may fetch a target command from a host based on a delay time of a function corresponding to the target command.