PCIe Root Port Timer Recalibration for Thunderbolt ASPM Handshake

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Solution Overview

Problem

The integration of PCIe tunneling over Thunderbolt (TBT) technology introduces packet throttling, which disrupts the Active State Power Management (ASPM) L1 handshake mechanism, leading to out-of-sync PCIe ports and inefficient power management, particularly due to dynamic latency and static latency introduced by the Thunderbolt host controller.

Innovation Solution

Recalibrated L1 timer values are implemented for the PCIe root port controller and upstream port to accommodate the static and dynamic latencies caused by the Thunderbolt host controller, ensuring safe windows for L1 request sampling and re-requests, and a halt indication signal is used to prevent spurious replays and optimize packet transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If PCIe tunneling is implemented over Thunderbolt, then multi-protocol support and cost effectiveness are improved, but packet throttling disrupts ASPM L1 handshake and causes out-of-sync PCIe ports

Engineering Contradiction:

Improvemulti-protocol supportVSAvoidASPM L1 handshake reliability

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent applies preliminary action by implementing timer recalibration before ASPM L1 negotiation failures occur. The system proactively adjusts timer values to account for Thunderbolt packet throttling latency, preventing the out-of-sync condition that would otherwise cause handshake failures. This is achieved by modifying the L1 timer values in the PCIe root port controller and upstream port to compensate for the dynamic latency introduced by Thunderbolt packet throttling.

Inventive Principle:

Principle #10Preliminary action

2Productivity

If packet throttling is used to manage bandwidth, then bandwidth control is improved, but dynamic latency causes timer timeout issues and spurious replays

Engineering Contradiction:

Improvebandwidth management efficiencyVSAvoidtimer timeout delay

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent applies parameter changes by recalibrating timer values to match the actual latency characteristics of the Thunderbolt interface. Specifically, the L1 timer values are adjusted to account for the dynamic latency introduced by packet throttling. This ensures that timer timeouts occur at appropriate moments in the ASPM negotiation process, preventing spurious replays while maintaining effective bandwidth management through packet throttling.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent implements feedback mechanisms through the halt indication signal that provides real-time information about packet transmission status. This feedback loop allows the system to detect when packets are being throttled and adjust timer behavior accordingly, preventing premature timeouts and ensuring accurate timing in the ASPM L1 negotiation process.

Inventive Principle:

Principle #23Feedback

3Reliability

If L1 timer values are recalibrated, then power management reliability is improved, but device complexity increases

Engineering Contradiction:

Improvepower management reliabilityVSAvoidcontroller complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies merging by integrating the timer recalibration functionality directly into the existing PCIe root port controller and Thunderbolt host controller. Rather than adding a separate recalibration module, the system combines the latency compensation logic with the existing ASPM negotiation logic, reducing overall system complexity while improving power management reliability.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS11132319B2Timer control for peripheral component interconnect express components implemented with thunderbolt controllers

Publication Date: 2021.09.28 INTEL CORP

AI summary

Aspects of the embodiments are directed to systems, methods, and devices for controlling power management entry. A PCIe root port controller can be configured to receive, at a downstream port of the root port controller, from an upstream switch port, a first power management entry request; reject the first power management entry request; transmit a negative acknowledgement message to the upstream switch port; initiate a timer for at least 20 microseconds; during the 20 microseconds, ignore any power management entry requests received from the upstream switch port; receive, after the expiration of the 20 microseconds, a subsequent power management entry request; accept the subsequent power management entry request; and transmit an acknowledgement of the acceptance of the subsequent power management entry request to the upstream switch port.