PCIe Time Processing Device for Low-Latency Clock Sync
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Solution Overview
Problem
Current time synchronization methods in data processing systems face challenges with accuracy due to high latency and susceptibility to operating system preemption, especially when using proprietary devices with low bandwidth interfaces, which are also expensive and require complex software propagation.
Innovation Solution
A dedicated time processing device is embedded within a data processing system's peripheral bus, utilizing a high-speed PCIe interface to receive and decode high precision time from a GPS source, storing it in internal time registers and allowing low-latency retrieval for system clock synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If proprietary NTP server devices are used, then time synchronization capability is provided, but device cost becomes very expensive
Solution Approach 1:
The patent uses a standard PCIe device as a copy/alternative to proprietary NTP server devices, implementing time synchronization functionality through a time processing device that interfaces with GPS time sources via standard PCIe bus, eliminating the need for expensive proprietary hardware while maintaining synchronization capability
Solution Approach 2:
The time processing device is designed as a universal component that can be integrated into standard PCIe bus architectures, making it adaptable to various computer systems without requiring proprietary specialized hardware, thus reducing cost while maintaining functionality
2Reliability
If software is used to propagate time, then time distribution is achieved, but latency increases due to multiple instructions and OS preemption
Solution Approach 1:
The patent replaces the software-based time propagation mechanism with a hardware-based PCIe interface and time processing device. The PCIe bus provides direct hardware access to the system clock, eliminating software instruction execution and OS scheduler preemption, thus dramatically reducing latency while maintaining time distribution capability
Solution Approach 2:
The time processing device acts as an intermediary between the GPS time source and the system clock, using the PCIe bus as a high-speed communication channel that bypasses software layers, thereby reducing latency while achieving accurate time distribution
3Device complexity
If low bandwidth serial interfaces are used, then device complexity is reduced, but time synchronization speed becomes slow
Solution Approach 1:
The patent changes the bandwidth parameter of the interface from low bandwidth serial (e.g., RS-232) to high bandwidth PCIe interface. This parameter change increases the data transmission speed significantly, enabling fast time synchronization while maintaining relatively simple device integration through standard bus architecture
Data Source
AI summary
In one embodiment, a dedicated time processing device inserted into a peripheral bus coupling or embedded with at least some of the rest of system components (e.g., processor, memory) of a data processing system to synchronize a system clock of the data processing system. The peripheral bus can be a Peripheral Component Interface (PCI) bus, a PCI Express (PCIe) link, a PCI extended (PCI-X) bus, or the like. The time processing device receives high precision time from a high precision time source, such as global positioning system (GPS) time source. The time processing device decodes and processes the received time and stores the time in an internal time register. The time processing device further includes an interface to allow an external component (e.g., a processor) to retrieve with low latency the time stored in the time register for the purpose of synchronizing the system clock.