PCIe Transaction Layer Circuit Parallel TLP Processing
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Solution Overview
Problem
Existing PCIe technologies face challenges in processing multiple transaction layer packets (TLPs) within the same clock cycle, which affects data transfer efficiency.
Innovation Solution
A transaction layer circuit for PCIe that includes multiple processing channels, a channel selection circuit, and a merge circuit, allowing for the simultaneous processing and merging of TLPs in the same clock cycle by distributing packet data based on start and end location information received from the data link layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple TLPs are transmitted in the same clock cycle, then data transfer efficiency is improved, but processing complexity increases
Solution Approach 1:
The patent divides the processing system into multiple independent processing channels (first processing channel, second processing channel, etc.), each capable of handling TLPs independently. The channel selection circuit segments the incoming TLP stream and distributes packets to appropriate channels based on packet start location information, enabling parallel processing of multiple TLPs simultaneously received in the same clock cycle.
Solution Approach 2:
The patent introduces a merge circuit as an intermediary component that receives processed TLPs from multiple processing channels and merges them back into a unified output stream. This mediator handles the complexity of coordinating multiple parallel channels, managing packet reassembly, and ensuring correct ordering, thereby isolating the complexity from the main processing flow.
2Productivity
If multiple processing channels are used to handle multiple TLPs, then processing capacity is improved, but channel management complexity increases
Solution Approach 1:
The channel selection circuit performs preliminary actions by pre-distributing incoming TLPs to appropriate processing channels based on packet start location information before the actual processing occurs. This advance organization and assignment simplifies the management of multiple channels during processing, as each channel receives its designated packets in advance rather than requiring complex real-time coordination.
Solution Approach 2:
The merge circuit implements feedback mechanisms to monitor the processing status of multiple channels and dynamically adjust the merging process. By receiving feedback from each processing channel about packet processing completion and status, the merge circuit can coordinate the recombination of TLPs from different channels, ensuring proper ordering and handling without requiring complex centralized control.
Data Source
AI summary
The invention provides a transaction layer circuit of a PCIe. The transaction layer circuit includes transaction layer processing channels, a channel selection circuit, and a merge circuit. The transaction layer processing channels are coupled to a data bus transmitting at least one packet data output by a data link layer circuit of the PCIe. The channel selection circuit receives packet start/end location information in a current clock cycle from the data link layer circuit, and distributes at least one packet data in the current clock cycle to at least one transaction layer processing channel according to the packet start/end location information. The merge circuit is coupled to the transaction layer processing channels and selectively merges transaction layer processing results output by the transaction layer processing channels based on the distribution of the packet data in the current clock cycle to the transaction layer processing channels via the channel selection circuit.