PCIe Traffic Tracking Hardware for Unified Virtual Memory
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Solution Overview
Problem
In multiprocessor systems, identifying frequent shared memory page accesses is inefficient due to performance reductions during measurement intervals caused by servicing page faults, which hampers the migration of shared memory pages from one processor's memory space to another.
Innovation Solution
A method involving an access tracking unit that uses a cache memory to increment access counters for accessed memory pages, dynamically allocates cache entries, and sets a threshold to identify frequently accessed pages for potential migration without inducing page faults, thereby improving the efficiency of shared memory page migration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If page faults are serviced to count memory page accesses during a measurement interval, then access frequency information can be obtained, but processor performance is reduced due to computing time needed to service page faults
Solution Approach 1:
An access tracking unit is introduced as an intermediary component that monitors and counts memory page accesses without requiring the processor to service page faults. The tracking unit intercepts access requests and updates access counters in cache memory, allowing accurate measurement of access frequencies while the processor continues normal operations without performance degradation.
Solution Approach 2:
The patent replaces the software-based page fault servicing mechanism with a hardware-based access tracking system. Instead of using operating system page fault handlers to count accesses, a dedicated hardware tracking unit with cache memory and counters directly monitors access patterns, eliminating the performance overhead associated with software page fault processing.
2Loss of time
If shared memory pages are migrated from one processor's memory space to another, then access latency is reduced for frequently accessed pages, but the complexity of memory management increases
Solution Approach 1:
The access tracking unit provides continuous feedback about memory access patterns to the memory management system. By monitoring access counters that record how frequently each page is accessed, the system can automatically identify candidate pages for migration and initiate migration decisions based on objective performance data, reducing the complexity of manual memory management while achieving latency optimization.
Solution Approach 2:
The system performs preliminary tracking and analysis of access patterns before initiating page migration. Access counters accumulate statistics during normal operation, and only when migration criteria are met does the system act to migrate pages. This preliminary measurement phase allows informed migration decisions that reduce access latency without premature or unnecessary migration operations.
3Productivity
If access counters are maintained in cache memory with dynamic entry allocation, then tracking efficiency is improved, but cache memory management complexity increases
Solution Approach 1:
The cache memory structure employs dynamic entry allocation where cache entries are allocated and deallocated based on actual access patterns. The access tracking unit can allocate new cache entries for frequently accessed pages and invalidate entries for pages that are no longer frequently accessed, allowing the cache to adapt dynamically to changing workload characteristics and maintain high tracking efficiency.
Solution Approach 2:
The system changes the state parameters of cache entries dynamically - setting valid bits to indicate allocated entries and clearing them for invalidation. This parameter-based management allows efficient tracking of which cache entries are in use without requiring complex data structures, simply by manipulating status bits in the cache entry format.
Data Source
AI summary
Techniques are disclosed for tracking memory page accesses in a unified virtual memory system. An access tracking unit detects a memory page access generated by a first processor for accessing a memory page in a memory system of a second processor. The access tracking unit determines whether a cache memory includes an entry for the memory page. If so, then the access tracking unit increments an associated access counter. Otherwise, the access tracking unit attempts to find an unused entry in the cache memory that is available for allocation. If so, then the access tracking unit associates the second entry with the memory page, and sets an access counter associated with the second entry to an initial value. Otherwise, the access tracking unit selects a valid entry in the cache memory; clears an associated valid bit; associates the entry with the memory page; and initializes an associated access counter.